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author | Alexander Goncharov <chat@joursoir.net> | 2022-08-11 21:47:13 +0300 |
---|---|---|
committer | Anastasia Klimchuk <aklm@chromium.org> | 2022-08-30 10:13:47 +0000 |
commit | 3234e04743ebcfed542ec7c551fd17435c5cbc1a (patch) | |
tree | 4664333b922b8b0d18fa9ab26f42fd8b3fdd0059 /nicintel_eeprom.c | |
parent | 95b6cf183522870d65a6aa34cab0c9a2b2f0870e (diff) | |
download | flashrom-3234e04743ebcfed542ec7c551fd17435c5cbc1a.tar.gz flashrom-3234e04743ebcfed542ec7c551fd17435c5cbc1a.tar.bz2 flashrom-3234e04743ebcfed542ec7c551fd17435c5cbc1a.zip |
nicintel_eeprom: refactor i210 variable into reentrant pattern
Move global Intel I210 specific variable into a struct and store
within the opaque_master data filed for the life-time of the driver.
This is one of the steps on the way to move opaque_master data
memory management behind the initialisation API.
TOPIC=register_master_api
TEST=builds
Change-Id: Ifda0d8666399ea165bac6378c57720b5560806f1
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Ticket: https://ticket.coreboot.org/issues/391
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66690
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'nicintel_eeprom.c')
-rw-r--r-- | nicintel_eeprom.c | 23 |
1 files changed, 18 insertions, 5 deletions
diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c index 0b06913c2..1cbb6bb15 100644 --- a/nicintel_eeprom.c +++ b/nicintel_eeprom.c @@ -73,13 +73,15 @@ static uint8_t *nicintel_eebar; static struct pci_dev *nicintel_pci; -static bool done_i20_write = false; #define UNPROG_DEVICE 0x1509 struct nicintel_eeprom_data { /* Intel 82580 variable(s) */ uint32_t eec; + + /* Intel I210 variable(s) */ + bool done_i20_write; }; /* @@ -219,7 +221,8 @@ static int nicintel_ee_write_word_i210(unsigned int addr, uint16_t data) static int nicintel_ee_write_i210(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) { - done_i20_write = true; + struct nicintel_eeprom_data *opaque_data = flash->mst->opaque.data; + opaque_data->done_i20_write = true; if (addr & 1) { uint16_t data; @@ -400,11 +403,12 @@ static int nicintel_ee_erase_82580(struct flashctx *flash, unsigned int addr, un return nicintel_ee_write_82580(flash, NULL, addr, len); } -static int nicintel_ee_shutdown_i210(void *arg) +static int nicintel_ee_shutdown_i210(void *opaque_data) { + struct nicintel_eeprom_data *data = opaque_data; int ret = 0; - if (!done_i20_write) + if (!data->done_i20_write) goto out; uint32_t flup = pci_mmio_readl(nicintel_eebar + EEC); @@ -421,6 +425,7 @@ static int nicintel_ee_shutdown_i210(void *arg) msg_perr("Flash update failed\n"); out: + free(data); return ret; } @@ -511,7 +516,15 @@ static int nicintel_ee_init(void) if (!nicintel_eebar) return 1; - return register_opaque_master(&opaque_master_nicintel_ee_i210, NULL); + struct nicintel_eeprom_data *data = calloc(1, sizeof(*data)); + if (!data) { + msg_perr("Unable to allocate space for OPAQUE master data\n"); + return 1; + } + data->eec = eec; + data->done_i20_write = false; + + return register_opaque_master(&opaque_master_nicintel_ee_i210, data); } return 1; |