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* util/manibuilder/README.md: Fix typoAngel Pons2021-03-231-1/+1
| | | | | | | | Change-Id: I68d3055d0d6b80b79673f66769663387fe15dcde Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/51518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* meson: Generalise libflashrom product to link as static or dynDaniel Campello2021-03-191-1/+1
| | | | | | | | | | | Allow the user to specify if they would like a static archive or a DSO produced for libflashrom by way of the flag e.g. `-Ddefault_library=static`. Signed-off-by: Daniel Campello <campello@chromium.org> Change-Id: I77e5c298163979a0222270b3ac5d03542e5618f7 Reviewed-on: https://review.coreboot.org/c/flashrom/+/51616 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* meson: Add print_wiki optionDaniel Campello2021-03-192-0/+7
| | | | | | | | | | | Align meson options to be equivalent to the Makefile as they are used in Gentoo's ebuilds. Signed-off-by: Daniel Campello <campello@chromium.org> Change-Id: I97d2fd687aa21533b86f9af446038bfe3da1f7d3 Reviewed-on: https://review.coreboot.org/c/flashrom/+/51552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* meson: fix dependency on raw accessDaniel Campello2021-03-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is matching the following comment on Makefile: \# This is a dirty hack, but it saves us from checking all PCI drivers and all platforms manually. \# libpci may need raw memory, MSR or PCI port I/O on some platforms. \# Individual drivers might have the same needs as well. This changes fixes: ld.lld: error: undefined symbol: rget_io_perms >>> referenced by internal.c:243 (../flashrom-9999/internal.c:243) >>> libflashrom.so.1.0.0.p/internal.c.o:(internal_init) ld.lld: error: undefined symbol: mmio_writeb >>> referenced by internal.c:122 (../flashrom-9999/internal.c:122) >>> libflashrom.so.1.0.0.p/internal.c.o:(internal_chip_writeb) ld.lld: error: undefined symbol: mmio_writew >>> referenced by internal.c:128 (../flashrom-9999/internal.c:128) >>> libflashrom.so.1.0.0.p/internal.c.o:(internal_chip_writew) ld.lld: error: undefined symbol: mmio_writel >>> referenced by internal.c:134 (../flashrom-9999/internal.c:134) >>> libflashrom.so.1.0.0.p/internal.c.o:(internal_chip_writel) ld.lld: error: undefined symbol: mmio_readb >>> referenced by internal.c:140 (../flashrom-9999/internal.c:140) >>> libflashrom.so.1.0.0.p/internal.c.o:(internal_chip_readb) ld.lld: error: undefined symbol: mmio_readw >>> referenced by internal.c:146 (../flashrom-9999/internal.c:146) >>> libflashrom.so.1.0.0.p/internal.c.o:(internal_chip_readw) ld.lld: error: undefined symbol: mmio_readl >>> referenced by internal.c:152 (../flashrom-9999/internal.c:152) >>> libflashrom.so.1.0.0.p/internal.c.o:(internal_chip_readl) ld.lld: error: undefined symbol: mmio_readn >>> referenced by internal.c:158 (../flashrom-9999/internal.c:158) >>> libflashrom.so.1.0.0.p/internal.c.o:(internal_chip_readn) ld.lld: error: undefined symbol: physmap >>> referenced by flashrom.c:1454 (../flashrom-9999/flashrom.c:1454) >>> libflashrom.so.1.0.0.p/flashrom.c.o:(probe_flash) >>> referenced by flashrom.c:1454 (../flashrom-9999/flashrom.c:1454) >>> libflashrom.so.1.0.0.p/flashrom.c.o:(probe_flash) >>> referenced by flashrom.c >>> libflashrom.so.1.0.0.p/flashrom.c.o:(programmer_table) >>> referenced 2 more times ld.lld: error: undefined symbol: physunmap >>> referenced by flashrom.c >>> libflashrom.so.1.0.0.p/flashrom.c.o:(programmer_table) >>> referenced by flashrom.c >>> libflashrom.so.1.0.0.p/flashrom.c.o:(programmer_table) >>> referenced by flashrom.c >>> libflashrom.so.1.0.0.p/flashrom.c.o:(programmer_table) Change-Id: Id3fa4ec7a735b81e989ba9fe2b53b18d0956627a Signed-off-by: Daniel Campello <campello@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/51577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Richard Hughes <hughsient@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* rayer_spi.c: Remove forward-declarationsAnastasia Klimchuk2021-03-181-54/+45
| | | | | | | | | | | | | | | | Reorder functions to avoid forward-declarations. This was aimed to be done for all spi masters in the earlier patch however this file was missed. BUG=b:140394053 TEST=builds Change-Id: I0e3c82967a169d6a2512ffa17d1e0c78eafb2797 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/51555 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* manibuilder: Add NetBSD 8.2 target (anita:8.2-amd64)Nico Huber2021-03-162-5/+11
| | | | | | | | | | | It needs more disk space and RAM. Also, make it the default as NetBSD 7.1 packages are gone. Change-Id: Ic823cd30228f15859462844eb50d213487f74873 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/51481 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* manibuilder: Add a version number to anita tagsNico Huber2021-03-162-10/+10
| | | | | | | | | | | | | | | | NetBSD 7.1 mirrors have dropped its packages, so we need something new and more flexibility. As we have always used NetBSD 7.1 so far, prepend the tags with `7.1-`. To avoid re-building old images, one can re-tag them, e.g.: $ docker image tag mani/anita:amd64 mani/anita:7.1-amd64 Change-Id: I44351805abab93c666d1d12c2bb17380caa75cec Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/51480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* manibuilder/anita: Make disk and memory sizes configurableNico Huber2021-03-162-2/+10
| | | | | | | | Change-Id: I95e428a19b4c2042430d3147845397adb1c37e9b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/51479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* manibuilder: Add list of tags used for the 1.1.x branchNico Huber2021-03-161-2/+55
| | | | | | | | | Change-Id: I243aa11f4a017a4209efcc227cec56eb12020e28 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33340 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* manibuilder: Add newer targets for Alpine, CentOS, FedoraNico Huber2021-03-161-2/+8
| | | | | | | | | Change-Id: I6c9939601abd3bd67424b8fa9a5ec800e50e3a51 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33342 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* manibuilder: Allow warnings in NetBSD and CentOS buildsNico Huber2021-03-161-1/+2
| | | | | | | | | | | Their old compilers stumble because of `-Wmissing-braces`. Change-Id: Ia9ee17fd1f0c8b191091f89ffbf44329c6521d7d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33339 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* manibuilder: Add libjaylink where possible, disable where notNico Huber2021-03-164-4/+10
| | | | | | | | | Change-Id: I2f7aebe602ebdb0a4748640e281b9a92146f0ca8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33338 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* manibuilder: Enable CONFIG_EVERYTHING=yesNico Huber2021-03-161-2/+3
| | | | | | | | | Change-Id: I4651b55744d730956aa8fda8fdfccbbd68cdda19 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33337 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* manibuilder: Add list of tags used for the 1.0.x branchNico Huber2021-03-161-2/+55
| | | | | | | | | | | Also add two new make targets `1.0.x` and `show-1.0.x`. Change-Id: I2bc2e79729016a8f9908f316b051deeb73dc096f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/30418 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add ManibuilderNico Huber2021-03-1613-0/+470
| | | | | | | | | | | | | | | | | | | Add a set of Dockerfiles for build testing. If you have an x86 machine and ~20GiB free disk space, run `make register` and `make -jxx` in util/manibuilder and go eat some pizza. The former runs a privileged docker container to set binfmt_misc up for qemu (read the code, don't trust it). Regarding the build targets, this is the original state of Manibuilder as it was used to build-test `flashrom-1.0`. Some fixes to the frame- work were applied, but fixups for the targets will be done in separate patches to maintain their original state for reference. Change-Id: I60863a5c7d70dde71486fccb66cb59b30ba4d982 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/23005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* cbtable.c: Use correct format specifier for `size_t`Angel Pons2021-03-161-1/+1
| | | | | | | | | | | Fixes building on 32-bit x86 systems. Change-Id: I8d798804f8055cdaff45f123e4f0d6ab4b71ba60 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/51478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* chipset_enable.c: Add PCI ID for Comet Lake U BaseSam McNally2021-03-111-0/+1
| | | | | | | | | | | TEST=`flashrom -r` on a kindred chromebook with a Celeron 5205U. Change-Id: I627dcacdad167343287ac0ec26b47505c2f823ee Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/51401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* CHROMIUM: flashrom: update .tested field for EN25QH128Tim Chen2021-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | update .tested field from TEST_UNTESTED to TEST_OK_PREW BUG=b:159768722 BRANCH=none TEST=Flash Duffy bios pass on running `flashrom_tester /usr/sbin/flashrom host` Original-Change-Id: I9467588988c2cab0987737c53ace0832144ef169 Original-Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2281508 Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Original-Commit-Queue: Edward O'Callaghan <quasisec@chromium.org> (cherry picked from commit 045e05eb92e3dd826e8ce61973c0d1004195a3ff) Change-Id: Ic111f1a9cc5c7b5b5100ddda362c11c91e8a4165 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* usb_device: Fix up whitespaceAngel Pons2021-03-102-21/+21
| | | | | | | | | | | | | Drop unnecessary spaces and indent with tabs, as per the coding style. TEST=Build with `make distclean && make VERSION=none -j` with and without this patch, the flashrom executable does not change. Change-Id: I200ace750dbe3c8d99f792d70a85b2ebd4e5b0ce Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/51115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* usb_device.h: Improve `LIBUSB_ERROR` macroAngel Pons2021-03-101-1/+1
| | | | | | | | | | | | | Guard macro parameters and correct a typo in the parameter name. TEST=Build with `make distclean && make VERSION=none -j` with and without this patch, the flashrom executable does not change. Change-Id: Ifc917b001713bc96adee46019d267f2090ef184a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/51114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* chipset_enable: Mark Intel C216 as DEPJacob Garber2021-02-281-1/+1
| | | | | | | | | | Tested reading and writing internal flash on HP Z220 SFF. Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I97538577c32e6c40374c414f005eb3165ed2e11d Reviewed-on: https://review.coreboot.org/c/flashrom/+/50986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Add support for Adesto AT25SF128AEdward O'Callaghan2021-02-282-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following adds support for the Adesto AT25SF128A-SHB-T part. We have varied the correct chip name is reported as well as write and read 16MBytes of random data and verified the checksum's match. Further, --wp-list appears to report the correct ranges. BUG=None BRANCH=none TEST=Ran flashrom with a Dediprog SF100, RW random data and checksum matched. Original-Change-Id: Ic22ca588f33753fdf492e8445324bcc0a809d3e2 Original-Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/1593201 Original-Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Original-Tested-by: Martin Roth <martinroth@chromium.org> Original-Reviewed-by: Martin Roth <martinroth@chromium.org> (cherry picked from commit 1fa87e058b72a2de1e9127a45e9978361de48479) Note: this does not include the changes made to writeprotect.c in the original patch, as they depend on a large amount of additional writeprotect code that is currently only present in the cros tree, and the intention here is just to reduce the diff in flashchips.c. The `.wp` field has also been removed. Change-Id: I1ce2a6699a1f0116306f668123673a1ba9c932d2 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/51097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* tree: Remove forward-declarations for spi mastersAnastasia Klimchuk2021-02-165-462/+432
| | | | | | | | | | | | | | | | | Reorder functions to avoid forward-declarations. It looks like for most of the spi masters this has already been done before, I covered remaining small ones in one patch. BUG=b:140394053 TEST=builds Change-Id: I23ff6b79d794876f73b327f18784ca7c04c32c84 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/50711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* serprog.c: Remove forward-declarationsAnastasia Klimchuk2021-02-161-239/+222
| | | | | | | | | | | | | | | Reorder functions to avoid forward-declarations BUG=b:140394053 TEST=builds Change-Id: I6d05b2ad7b1a753aa752b22f9eb60a7b37dff641 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/50713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* dummyflasher.c: Remove forward-declarationsAnastasia Klimchuk2021-02-161-450/+438
| | | | | | | | | | | | | | | Reorder functions to avoid forward-declarations BUG=b:140394053 TEST=builds Change-Id: Ibfe9f556316ed509cbec522b4c9cb4c9041e5fdd Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/50712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* realtek_mst_i2c_spi.c: Move gpio 88 toggle outside write functionShiyu Sun2021-02-121-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Gpio 88 toggle is used as write protection disable/enable now and we need that to happen at the initialization of programmer. Background: The RTD devices has an interesting implementation where the flag we need to flash is `aa aa aa ff ff`. However, after reset, the boot firmware of RTD device will overwrite this flag value to `aa aa aa ff aa`. Given this evidence, the root cause would be that the boot firmware is doing something with protection enable by itself. This explains why the message 'Block protection cannot be disabled' is shown since the block protection is called before write operation. BUG=b:147402710,b:152558985,b:178766553 BRANCH=none TEST=flashrom -p realtek_mst_i2c_spi:bus=x,reset-mcu=1,enter-isp=1 -w image.bin Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: I237bf9f8aa0fcbb904e7f0c09c74fd179e8c70c1 Reviewed-on: https://review.coreboot.org/c/flashrom/+/49785 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* CHROMIUM: avl_tool: more gracefully handle termination by SIGINTPeter Marheine2021-02-114-1/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | Since interrupting the test process may be dangerous (leaving the flash in an inconsistent state), we'll catch SIGINT and print a warning the first time, also using it as a signal that we should stop at a convenient time. Any following SIGINT will be handled as normal (killing the process). BUG=b:143251344 TEST=Run tool and verify it exits after a test with a single ^C, exits immediately given two. BRANCH=None Original-Cq-Depend: chromium:2059548 Original-Change-Id: Ib8a7799cba6dbca57dc7f1d3c87521f132c21818 Original-Signed-off-by: Peter Marheine <pmarheine@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2050050 Original-Tested-by: Edward O'Callaghan <quasisec@chromium.org> Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Change-Id: If43aea0580fcc7e698daad2ffe085a3c9da5bc41 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/49915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips: Mark Macronix MX25L1635D as testedAngel Pons2021-02-071-1/+1
| | | | | | | | | | Tested probe, read, erase and write with a FTDI FT2232H successfully. Change-Id: I7421b7e36e687ea2ffff494c00157976db73ac43 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/49489 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jlink_spi: Reduce transfer sizeMarc Schink2021-02-071-1/+1
| | | | | | | | | | | | The maximum transfer size is too large for some devices and results in an USB timeout. Change-Id: If2c00b1524ec56740bdfe290096c3546cf375d73 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Miklós Márton <martonmiklosqdev@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Fix building with musl libcEvgeny Zinoviev2021-02-071-1/+1
| | | | | | | | | | | | AFAIK, this shouldn't break anything, as glibc just includes fcntl.h from sys/fcntl.h. Change-Id: Ie74ae584619ae8cbc188855aedcf5596d7afcfc8 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* linux_mtd: Disable buffering on the mtd deviceDouglas Anderson2021-02-011-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We open the device node for the MTD device with this: dev_fp = fopen(dev_path, "r+") In C fopen() is allowed to provide _buffered_ access to the file. That means that the standard library is allowed to read ahead and/or return cached data. That's really not what we want for something like this. Let's turn it off. This fixes a problem where flashrom would sometimes fail to "verify" that it erased the flash. The error message would look something like this: Erasing and writing flash chip... FAILED at 0x0000e220! Expected=0xff, Found=0xe9, failed byte count from 0x0000e200-0x0000e2ff: 0xdc failed byte count from 0x0000e000-0x0000efff: 0xffffffff ERASE_FAILED FAILED! Uh oh. Erase/write failed. Checking if anything changed. After the failure I could read the flash device with a new invocation of flashrom and I would see that, indeed, the erase had worked. Tracing in the kernel showed that when the failure happened we saw a pattern that looked like this: * Read 0x0b00 bytes starting at 0x0000d000 * Read 0x1000 bytes starting at 0x0000db00 * Erase 0x1000 bytes starting at 0x0000e000 ...and then there was _not_ a read after the erase. It can be assumed that, since userspace had already read 0xdb00 - 0xeaff that it was looking at old buffered data after the erase. Signed-off-by: Douglas Anderson <dianders@chromium.org> Change-Id: I989afd83a33013b2756a0090d6b08245613215c6 Reviewed-on: https://review.coreboot.org/c/flashrom/+/50155 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* realtek_mst_i2c_spi.c: Skip return value check for reset functionShiyu Sun2021-01-281-3/+7
| | | | | | | | | | | | | | | The return value for reset function can not be guaranteed when reset success. There is no way to check if reset success or not. BUG=b:147402710,b:152558985 BRANCH=none TEST=builds Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: Ia6200f7150db4368c26d8dfe779a9e85184b1b06 Reviewed-on: https://review.coreboot.org/c/flashrom/+/49786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* meson.build: Require at least meson 0.50.0Angel Pons2021-01-281-1/+1
| | | | | | | | | | | | | | | | The `install` argument in `configure_file` is a feature introduced in meson '0.50.0', but meson.build requests '>=0.47.0'. Meson complains: WARNING: Project targeting '>=0.47.0' but tried to use feature introduced in '0.50.0': install arg in configure_file. To correct this, adjust the `meson_version` value accordingly. Change-Id: Iadcffb7f8c720ffa8aa5f0ad62638d7b37f39934 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/49924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* meson: Rename 'config_raiden' to 'config_raiden_debug_spi'Edward O'Callaghan2021-01-272-4/+4
| | | | | | | | | | | | | | | Make meson build option name consistent with the the spi masters implementation name. BUG=none TEST=builds Change-Id: Icb6c73ab3d4369fcffb96eb117fc376da75dfb84 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/49914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sam McNally <sammc@google.com>
* cbtable.c: don't assume high addresses can fully map 1 MiBEdward O'Callaghan2021-01-251-8/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Forward port the downstream `commit b17e9e41838`. When using a forwarding table entry for finding the coreboot table don't assume one has access to a full 1 MiB where the forwarding table entry points to. The reason is that the 1 MiB may cover address regions that have differing cacheability type. As such the kernel will complain and the mapping will fail. Instead, check the header first then map in the bytes that it indicates after sanity validation. That way there is no attempt at requesting an invalid mapping that spans different memory cacheability attributes. V.2: Incorperate Nico's and Angels comments from upstream. BUG=b:66681446 BRANCH=None TEST=Can successfully run 'flashrom -p host --wp-status' on kahlee without generating PAT errors. Original-Change-Id: Ic6c5832b069300cced66e11f4ca4a0bbc6e496de Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/685608 Original-Reviewed-by: Martin Roth <martinroth@chromium.org> Original-Reviewed-by: Justin TerAvest <teravest@chromium.org> Change-Id: I43705c19dd7c816098d03f528bde6f180c4c8f24 Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/37240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* helpers.c: Fix undefined behavior in strndup()Xiang Wang2021-01-241-8/+9
| | | | | | | | | | | | | | Using strlen() or strdup() inside strndup() is problematic: if the input string is not null-terminated, these functions can read past the end of the buffer, which triggers undefined behavior. Rewrite the function to never read past the provided `maxlen` bound. Change-Id: Id34127024085879228626fbad59af03268ec5255 Signed-off-by: Xiang Wang <merle@hardenedliux.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/49741 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ft2232_spi.c: Rename cs_bits to pinlvlAlan Green2021-01-241-12/+12
| | | | | | | | | | | | Renames the variable cs_bits to pinlvl, to more accurately reflect its role. pinlvl works in conjunction with pindir to specify GPIO pin state. Signed-off-by: Alan Green <avg@google.com> Change-Id: I53d1ccae8fa870f037b03762bec79fee1b7bad21 Reviewed-on: https://review.coreboot.org/c/flashrom/+/49780 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ft2232_spi.c: Generalize GPIOL pin controlAlan Green2021-01-241-1/+43
| | | | | | | | | | | | | | | | | | Adds a new arg "gpiol" to allow the four FT2232 GPIOL pins to be set to any combination of high, low or high-impedance. The existing arg "csgpiol", is intended to function as an additional "cs" signal, allowing pins to be set high but not low. This patch preserves the csgpiol arg for backward compatibility. In the event that both arguments are specified, gpiol is used. Signed-off-by: Alan Green <avg@google.com> Change-Id: I1f2b3b968577e62e3c5b11bcdf4afe2de6eb84ab Reviewed-on: https://review.coreboot.org/c/flashrom/+/49637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Xiang Wang <merle@hardenedlinux.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ft2232_spi.c: release I/Os on shutdownAlan Green2021-01-241-0/+25
| | | | | | | | | | | | | | | | | | | | Reset FTDI I/O pins to high-Z (input) when shutting down. This allows other devices to use the SPI bus without having to disconnect the programmer. This change will introduce a backward incompatibility in the case where a user is relying on the state of FTDI outputs post-programming (eg. to disallow another device from driving CS low). However, there are likely more cases where releasing the SPI bus is the correct thing to do. Signed-off-by: Alan Green <avg@google.com> Change-Id: I9fae55e532595752983f55fac2298f81699dbe5b Reviewed-on: https://review.coreboot.org/c/flashrom/+/49632 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* programmer.h: remove unused declarationAlan Green2021-01-221-1/+0
| | | | | | | | | | | | | | Removes unused declaration of noop_shutdown(). The implementation was removed in 386cc556a4 and this declaration ought to have been removed at the same time. Signed-off-by: Alan Green <avg@google.com> Change-Id: I7599ace08f3635251a80612df4b4d29001f81d35 Reviewed-on: https://review.coreboot.org/c/flashrom/+/49800 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* realtek_mst_i2c_spi.c: Fix indentationShiyu Sun2021-01-221-3/+3
| | | | | | | | | | | | | BUG=none BRANCH=none TEST=builds Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: I730882c97926dfbe8b68b286c3805d6470993da8 Reviewed-on: https://review.coreboot.org/c/flashrom/+/49784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* it85spi.c: Inline it85xx_spi_common_init()Anastasia Klimchuk2021-01-211-52/+45
| | | | | | | | | | | | | | | | | Inline it85xx_spi_common_init() to single call site of it85xx_spi_init() as the construction is a single phase one. This allows for less cyclomatic complexity by validating early and initialisation at the eulogy of the one entry-point to the driver. BUG=b:172876667 TEST=builds Change-Id: Iac1b4ae9c6f34c5265e729ae0a80024800c3c272 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* programmer: remove unused noop_shutdown functionAlan Green2021-01-191-6/+0
| | | | | | | | | | | Function appears to be vestigial. Signed-off-by: Alan Green <avg@google.com> Change-Id: I1b67223aed8be54b60771aa1b2d498836ed28060 Reviewed-on: https://review.coreboot.org/c/flashrom/+/49631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* it85spi.c: Refactor singleton states into reentrant patternAnastasia Klimchuk2021-01-191-35/+49
| | | | | | | | | | | | | | | Move global singleton states into a struct and store within the spi_master data field for the life-time of the driver. BUG=b:172876667 TEST=builds Change-Id: I389d34d62e753c012910aa5ff24a496b24a4753c Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* util/getrevision.sh: Fallback when git tags is missingEdward O'Callaghan2021-01-181-1/+1
| | | | | | | | | | | | | | | If the tags are missing the version may not be evaluated correctly. BUG=b:177691209 BRANCH=none TEST=none Change-Id: Ib9f85b2be8b6f5e1332ba98a8a71fcad12331818 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/49618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* tree/: Drop const from opaque data ptr in master definitions [alt]Edward O'Callaghan2021-01-172-8/+15
| | | | | | | | | | | | | | | | | | The opaque data pointer need not necessarily have constant data for the life-time of the specific master. This is because the data field purpose is for the master to use as it sees fit for managing its own internal state and therefore we should not constrain this as being RO data at init time. BUG=none BRANCH=none TEST=builds Change-Id: I686c3c79547e35d48f3fd0b524fc98c176dcea6e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/49131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* flashchips.c: Mark GD25LQ128C/D as TEST_OK_PREWAlan Green2021-01-151-1/+1
| | | | | | | | | | | | I have successfully probed/read/erased/written a GD25LQ128D, so marking this entry as tested. Signed-off-by: Alan Green <avg@google.com> Change-Id: Ic5329ebe81b6c1eabfb594f7f7affb3fd460db6b Reviewed-on: https://review.coreboot.org/c/flashrom/+/49229 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Makefile: Explicitly set '-std=c99'Edward O'Callaghan2021-01-132-1/+3
| | | | | | | | | | | | | | | | | | This matches the build flags that are correctly explicitly defined in meson.build where-as the Makefile is randomly picking up whatever the system toolchain happens to default to. Fix dmi.c while we are here to avoid a re-define of _GNU_SOURCE. BUG=none TEST=`make` with both gcc and clang. Change-Id: I4f973927fc018510a3beaa6c4fa2f356c77c7a6e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47908 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25_statusreg.c: restore SR contents at flashrom exitNikolai Artemiev2021-01-131-0/+9
| | | | | | | | | | | | | | register_chip_restore() provides a general mechanism for restoring a chip's state at flashrom exit; it can be used whenever the SR needs to be changed temporarily to perform some operation and changed back after the operation is complete. The only current current use case is in s25f.c, which changes the SR's sector layout bits so that entire flash accessible. This patch uses the chip restore functionality to reset changes to the status register made by spi_disable_blockprotect_generic(). This should help to ensure consistency across multiple runs of flashrom and make it easier to predict how a specific operation will change the flash. Imported from cros flashrom at `b170dd4e1d5c33b169c5` Change-Id: If2f0e73518d40519b7569f627c90a34c364df47c Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Makefile: Add a DISABLE_CLOCK_GETTIME optionMartin Lucina2021-01-111-0/+5
| | | | | | | | | | | | | | Allows to force-disable the use of clock_gettime() at build time, falling back to busy-looping for udelay. This is useful when building for systems which are known to lie about the resolution of clock_gettime(), such as Linux guests running under the Muen Separation Kernel. Change-Id: I645a5d3f29ffdbd24a58127ab73d7d8755304f45 Signed-off-by: Martin Lucina <martin@lucina.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48796 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-15 19:43:56 +0000