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* printf: Use inttype.h macros for format stringsThomas Heijligen2023-04-271-28/+28
| | | | | | | | | | | | | | DJGPP for compiling DOS has other sizes for the normal int types and therefore throwing errors when using %i %d or %x with uint32_t. Fix these warnings by using the macros created for it and provided in inttypes.h. Change-Id: Ia75b6df981ce60c891161fe553c7ceab8570178d Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73040 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ich_descriptors.c: Retype variable `has_forbidden_opcode` with boolFelix Singer2022-09-081-3/+4
| | | | | | | | | | | | Use the bool type instead of an integer for the variable `has_forbidden_opcode`, since this represents its purpose much better. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I6214956e377547b894fc76237832b6f7b2db41dd Reviewed-on: https://review.coreboot.org/c/flashrom/+/66899 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ich_descriptors.c: Reduce i/o op paths in read_descriptor_reg()Edward O'Callaghan2022-08-081-4/+11
| | | | | | | | | | | | Simplify I/O operations to one path after all branch logic is complete. Work towards consolidated enum ich gen branch logic. Change-Id: I37d22217a7cfc4cffc4f6cfe7b1df6f30df3ca92 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Thomas Heijligen <src@posteo.de>
* ichspi: Add Intel Alder Lake-S supportMichał Kopeć2022-05-191-2/+6
| | | | | | | | | | | | Add ADL PCH-S device IDs to enable flashrom on Alder Lake-S platforms. TEST=Dump BIOS on MSI Z690 PRO DDR4 WIFI Change-Id: Ib2a8c057994874a41ed400b176f156048dae43c0 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* Global cleanup: Fix a few spelling errorsMartin Roth2022-05-031-2/+2
| | | | | | | | | | | | | | | | Just a trivial patch to fix a few errors found by codespell. Here's the command I used: codespell -S subprojects,out \ -L fwe,dout,tast,crate,parms,claus,nt,nd,te,truns,trun Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4e3b277f220fa70dcab21912c30f1d26d9bd8749 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62840 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi: Add Jasper Lake supportEdward O'Callaghan2022-04-141-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect the chipset when the CSSL (CPU Soft Strap Length) field default value (0x03) on Jasper Lake is the same as Elkhart Lake. BUG=b:221175960 TEST=dedede with `flashrom -p internal --flash-size`. ``` $ flashrom -VVV -p internal --ifd -i fd -i bios -r /tmp/filename.rom <snip> Enabling hardware sequencing by default for 100+ series PCH. OK. No board enable found matching coreboot IDs vendor="Google", model="Magolor". The following protocols are supported: Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Chip identified: GD25Q127C/GD25Q128C Hardware sequencing reports 1 attached SPI flash chip with a density of 16384 kB. There is only one partition containing the whole address space (0x000000 - 0xffffff). There are 4096 erase blocks with 4096 B each. Added layout entry 00000000 - 00ffffff named complete flash Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Reading Status register Block protection is disabled. Reading ich descriptor... Reading 4096 bytes starting at 0x000000. done. Assuming chipset 'Jasper Lake'. Added layout entry 00000000 - 00000fff named fd Added layout entry 00381000 - 00ffffff named bios Added layout entry 00001000 - 00380fff named me restore_power_management: Re-enabling power management. Using regions: "bios", "fd". Reading Status register Block protection is disabled. Reading flash... 0x381000-0xffffff:R Reading 13103104 bytes starting at 0x381000. 000000-0x0fff:R Reading 4096 bytes starting at 0x000000. done. restore_power_management: Re-enabling power management. SUCCESS Restoring PCI config space for 00:1f:5 reg 0xdc restore_power_management: Re-enabling power management. ``` Change-Id: Ib942d0b8942fe0a991b2af0b187414818485153d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sam McNally <sammc@google.com>
* ich_descriptors.c: Ensure unsigned types >=0 on to prevent underflowaarya2022-04-111-4/+5
| | | | | | | | | | | | Unsigned types show undefined behaviour if they are subtracted by a value greater than their own (mostly it wraps to the max value). Using this value for left shifting could be even more dangerous. Change-Id: I5921cc571f3dca5188ca1973dba6ececbcbe2f39 Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* ichspi: Add support for Meteor LakeSubrata Banik2022-03-301-4/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds Meteor Lake support into flashrom. Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect the chipset when the CSSL (CPU Soft Strap Length) field default value (0x03) on Meteor Lake is the same as Elkhart Lake. BUG=b:224325352 TEST=Flashrom is able to detect MTL SPI DID and show chipset name as below: > flashrom --flash-name .... Found chipset "Intel Meteor Lake-P/M". .... > flashrom - internal --ifd -i fd -i bios -r /tmp/bios.rom .... Reading ich_descriptor... done. Assuming chipset 'Meteor Lake'. Using regions: "bios", "fd". Reading flash... done. SUCCESS Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0a2ffe2ba8d96c90d89b77e0d8583d179ff02a75 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Sam McNally <sammc@google.com>
* ichspi: Add Alder Lake supportEdward O'Callaghan2022-03-071-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Does exactly what it says on the tin. BUG=b:220799648 TEST=```localhost ~ # flashrom --flash-name <snip> Found Programmer flash chip "Opaque flash chip" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000. vendor="Programmer" name="Opaque flash chip" flashrom -p internal --ifd -i fd -i bios -r /tmp/filename.rom flashrom unknown on Linux 5.15.22 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). coreboot table found at 0x768a7000. Found chipset "Intel Alder Lake-N". Enabling flash write... Warning: Setting BIOS Control at 0xdc from 0x8b to 0x89 failed. New value is 0x8b. SPI Configuration is locked down. OK. Found Winbond flash chip "W25Q256JV_M" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000 /dev/mem mmap failed: Resource temporarily unavailable Could not map flash chip W25Q256JV_M at 0x00000000fe000000. Reading ich descriptor... done. Using regions: "bios", "fd". Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000 /dev/mem mmap failed: Resource temporarily unavailable Could not map flash chip W25Q256JV_M at 0x00000000fe000000. Reading flash... done. SUCCESS Also, Reading ich descriptor... Reading 4096 bytes starting at 0x000000. done. Assuming chipset '600 series Alder Point'. Added layout entry 00000000 - 00000fff named fd Added layout entry 00500000 - 01ffffff named bios Added layout entry 00001000 - 004fffff named me ``` Tested on Nivviks/ADL-N and Brya/ADL-P. Change-Id: Ie66cf519df13f3391c41f5016b16a81ef3dfd4bf Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sam McNally <sammc@google.com>
* ich_descriptors.c Invert the meaning of 'dual_output' bitWerner Zeh2022-02-161-1/+1
| | | | | | | | | | | | | | | | | | In the Flash Component description register (FLCOMP) bit 30 reports the capability of using dual output for fast read operation on the flash component. According to various SPI Programming Guides (checked for Panther Point, Lewisburg C620, Apollo Lake and Elkhart Lake) the dual output is enabled when this bit is set and disabled if not. Currently the logic displays it the other way around when parsing the descriptor. This patch changes this so now if bit 30 in FLCOMP is not set, dual read support for fast read operation is shown as disabled. Change-Id: If6282ac8326ab0b92e9c70c09dba0299bf0deb6f Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/61362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Add Elkhart Lake supportWerner Zeh2022-02-041-4/+24
| | | | | | | | | | | | | | | | Elkhart Lake has a chipset called Mule Creek Canyon which is quite compatible with 300 series chipsets. There are a few differences though, e.g. different encoding for the SPI clock values for read and write in the FLCOMP register. In addition Elkhart Lake has a new PCI device ID for the SPI controller which is added, too. TEST=Read and flash complete flash on Siemens MC EHL1 Change-Id: I711e39a3ec9cd7098389231eaa1cb864d615a475 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/60711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* hwaccess: move mmio functions into hwaccess_physmapThomas Heijligen2022-01-201-1/+1
| | | | | | | | | | | The mmio_le/be_read/writex functions are used for raw memory access. Bundle them with the physmap functions. Change-Id: I313062b078e89630c703038866ac93c651f0f49a Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/61160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Add Tiger Lake U Premium supportMichał Żygowski2021-11-171-7/+56
| | | | | | | | | | | | | | | | | | | | | | Tiger Lake has very low ICCRIBA (TGL=0x11, CNL=0x34 and CML=0x34) and detects as unknown chipset compatible with 300 series chipset. Add a new enum CHIPSET_500_SERIES_TIGER_POINT and treat it identically to CHIPSET_400_SERIES_COMET_POINT. There are some exceptions though, ICCRIBA is no longer present n descriptor content so a new union has been defined for new fields and used in descriptor guessing. freq_read field is not present on Tiger Lake, moreover in CannonPoint and Comet Point this field is used as eSPI/EC frequency, so a new function to print read frequency has ben added. Finally Tiger lake boot straps include eSPI, so a new bus has been added for the new straps. TEST=Flash BIOS region on Intel i5-1135G7 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I28f3b6fe9f8ce9e976a6808683f46b6f4ec72bdd Reviewed-on: https://review.coreboot.org/c/flashrom/+/55578 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* hwaccess.c: move function declarations from programmer.h to hwaccess.hThomas Heijligen2021-11-071-0/+1
| | | | | | | | | | | | Move declarations for functions implemented in hwaccess.c from programmer.h to hwaccess.h. Change-Id: I075fd86211c766ae3d5f29c76adbd7c5b9bdbd80 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58865 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ich_descriptors: Add explicit checks for all chipsetsDavid Hendricks2021-10-011-10/+19
| | | | | | | | | | | | | | | | This partially undoes changes made in commit cd9b7b427 (ich_descriptors: Normalize chipset detection) to re-add explicit matching of each chipset with one or more strap length values. Since ranges are checked explicitly, the `warn_if` parameter to warn_peculiar_desc() is no longer necessary and is removed. Change-Id: Ica49477492876810a6fa212768b1ab9e8c12001f Signed-off-by: David Hendricks <ddaveh@amazon.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/57793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Add support for Intel Emmitsburg PCHJonathan Zhang2021-09-011-0/+2
| | | | | | | | | | | | | | | | | | | | This patch does the following: - Add PCIe ID for Intel Emmitsburg PCH - Based on ICH descriptor content, choose CHIPSET_C620_SERIES_LEWISBURG if ISL/PSL is 80. TESTED=tried on a server with Intel Emmitsburg PCH, flash update was successful. This server, however, does not have flash chip installed, it instead has em100 emulator connected. Change-Id: I2a1bb7467e693d1583aa885fa0e277075edd4a3e Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Tim Chu <Tim.Chu@quantatw.com>
* ich_descriptors: Normalize chipset detectionNico Huber2021-06-301-11/+7
| | | | | | | | | | | | | | | | Normalize the fallback paths: * Always end with the newest, assumed compatible chipset. * Perform tighter checks when it's about warnings only. * If two chipsets seem compatible, always return the same (this is currently the case for 8/9 series and 300/400 series which we can't distinguish). Change-Id: Ic5a5fee870202173b3a9813b03ec261e8ee45155 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55651 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ich_descriptors: Don't base chipset detection on `freq_read`Nico Huber2021-06-301-5/+3
| | | | | | | | | | | | | Only warn if the `freq_read` setting looks odd but don't override our previous guess. The `freq_read` check was taken from `ifdtool` but seems less reliable than our own detection scheme. Change-Id: I658d76ec2567d1d660a18d0b0ae71c744e603e8f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* ich_descriptors: Revise detection for chipsets w/ ICCRIBANico Huber2021-06-301-21/+24
| | | | | | | | | | | | | | | Detection based on ICCRIBA and FMSBA became a little messy lately. However, there's a new static difference: Since 300 series (Cannon Point), there is an MDTBA field in FLUMAP1 that has always been 0 (reserved) before. Taking this into account, we can relax the checks on ICCRIBA. Change-Id: I587ad1abe390843d4a9e74431b6fc4b63f8ba512 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* layout: Drop `count` parameter of flashrom_layout_new()Nico Huber2021-06-261-1/+1
| | | | | | | | | | Change-Id: I22c180c9971068b1ae101845ce88484c6842b852 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33544 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* layout: Introduce flashrom_layout_new()Nico Huber2021-06-261-6/+9
| | | | | | | | | | | | | | | | | It initializes an empty layout. Currently the maximum number of entries has to be specified, which will vanish once we use dynamic allocation per entry. We replace the two special cases `single_layout` and `ich_layout` with dynamically allocated layouts. As a result, we have to take care to release the `default_layout` in a flashctx once we are done with it. Change-Id: I2ae7246493ff592e631cce924777925c7825e398 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* layout: Introduce flashrom_layout_add_region()Nico Huber2021-06-261-11/+6
| | | | | | | | | | | | | Adds a region to an existing layout, as long as there is space. Change-Id: I50d473d0d5d1fb38bd6f9ae3d7127e9ea66a94e1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33517 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* layout: Add `capacity` fieldNico Huber2021-06-261-0/+1
| | | | | | | | | | | | | | Use it to keep track of the size of the `entries` array. An interim solution until we have dynamic allocation. Change-Id: Ib5f431bc0a72a79a53fa1376c3417942b19dd3a0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33516 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ich_descriptors: Refactor read_ich_descriptors_from_dump()Nico Huber2021-06-191-17/+17
| | | | | | | | | | | Process the "upper map" early as it doesn't depend on the descriptor generation. This way, we can use it to guess the generation. Change-Id: Ia2786b762ccefdce31b63397119bd89879e887ff Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ich_descriptors: Drop some unnecessary `else` after `return`Nico Huber2021-06-191-10/+8
| | | | | | | | | Change-Id: Id739bc12832e3b441e8e7e1dcdcc4c05b260d7ad Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55645 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ich_descriptors: Revise descriptor messagesNico Huber2021-06-191-7/+13
| | | | | | | | | | | | | Correct "firmware descriptor" to "flash descriptor". And also move the check for peculiar descriptors and the message into an inline function. Change-Id: I7f15780e03d2fa17ca6d8328275cae5af13ae424 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55644 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Fix up handling of IFD chipsetsAngel Pons2021-05-201-1/+2
| | | | | | | | | | | | | When `CHIPSET_400_SERIES_COMET_POINT` got added, the `chipset_names` table was not updated. Add the missing entry and reorder it to be next to `CHIPSET_300_SERIES_CANNON_POINT` for consistency. Change-Id: I4f4b31ecf91c432a2e82a92e274cb91ac166e635 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com>
* Add Gemini Lake supportAngel Pons2021-05-161-4/+14
| | | | | | | | | | | The SPI hardware is pretty much unchanged from Apollo Lake. However, the IFD differs significantly enough to require special handling. Signed-off-by: Angel Pons <th3fanbus@gmail.com> Change-Id: Ib5dcdf204166f44a8531c19b5f363b851d2ccd77 Reviewed-on: https://review.coreboot.org/c/flashrom/+/54276 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add support for Comet Lake-U/400-series PCHMatt DeVillier2020-09-241-1/+9
| | | | | | | | | | | | | | | | Add enum CHIPSET_400_SERIES_COMET_POINT and treat it identically to CHIPSET_300_SERIES_CANNON_POINT. Add PCI IDs for Comet Lake, CML-U Premium and classify as CHIPSET_400_SERIES_COMET_POINT. Test: read/write unlocked CML-U board Change-Id: I43b4ad1eecfed16fec59863e46d4e997fbe45f1b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/44420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* allow 0x34 as ICCRIBA for CHIPSET_C620_SERIES_LEWISBURGJonathan Zhang2020-09-101-3/+11
| | | | | | | | | | | | | | | | | Intel C621A Lewisburg PCH belongs to C620 series, it has 0x34 as ICCRIBA. Fix guess_ich_chipset_from_content() accordingly. Print status info of read_ich_descriptors_from_dump() to facilitate debugging upon failure. TESTED=run flashrom successfully from OCP Yosemite V3 DeltaLake server. Change-Id: I363aaccfb90e0a127c0f0bb0072e9e85c210b669 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/44621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Fix more sign-compare issuesNico Huber2019-10-051-1/+1
| | | | | | | | | | | | | The one in the `dummyflasher` is a little peculiar. We actually never knew the type of the `st_size` field in `struct stat`. It happens to be `signed` in some systems (e.g. DJGPP). Change-Id: If36ba22606021400b385ea6083eacc7b360c20c5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/35800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* ichspi: Add support for discrete Cannon Lake PCHsNico Huber2019-08-081-7/+34
| | | | | | | | | | | | | | | | Only minor differences in the Firmware Descriptor, compared to their predecessors. We extend our check on the `ICCRIBA` field in the descriptor to dis- tinguish it from older generation. Alas, the `freq_read` field was repurposed, so we can't use it as sanity check any more. Change-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* Fix -Wsign-compare troubleNico Huber2019-07-311-23/+20
| | | | | | | | | | | Mostly by changing to `unsigned` types where applicable, sometimes `signed` types, and casting as a last resort. Change-Id: I08895543ffb7a48058bcf91ef6500ca113f2d305 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/30409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
* ichspi: Add Apollo Lake supportNico Huber2019-07-061-22/+77
| | | | | | | | | | | | | | | It's almost identical to 100 series PCHs and later. There are some additional FREGs (12..15). To not clutter the `if` conditions further, make more use of `switch` statements. Tested on Kontron mAL10. Mark it as DEP as usually the last sector is not covered by the descriptor layout and can't be read. Change-Id: I1c464b5b3d151e6d28d5db96495fe874a0a45718 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/30995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* tree: Make internal functions staticJacob Garber2019-06-231-6/+6
| | | | | | | | | | | | None of these functions are used outside of the files they are defined in, so make them all static. Change-Id: Ie9cbe12d289bcedacf2f1bf483ae64ef8039ccc1 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
* layout: Make `romentry.name` a pointerNico Huber2019-06-171-2/+5
| | | | | | | | | | | This should provide more flexibility while we don't have to allocate 256B extra per layout entry. Change-Id: Ibb903113550ec13f43cbbd0a412c8f35fe1cf454 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* ich_descriptors: Drop line numbering commentsNico Huber2019-06-071-16/+16
| | | | | | | | | Change-Id: Ia895e35edfc86b6955395c4570d67477da70e2c7 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* Fix several -Wno-implicit-fallthrough warningsRichard Hughes2019-02-111-0/+2
| | | | | | | | | | | | GCC is picky about the comment being where the break should go. Change-Id: I05db2fb34025fefe2c6ddd1274c8e45b7cc5a4b6 Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/30406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Remove address from GPLv2 headersElyes HAOUAS2018-04-241-4/+0
| | | | | | | | Change-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* chipset_enable: Add support for C620-series Lewisburg PCHDavid Hendricks2017-09-011-19/+67
| | | | | | | | | | | | | | | | This adds PCI IDs for C620-series PCHs and adds CHIPSET_C620_SERIES_LEWISBURG as a new entry in the ich_chipset enum. Lewisburg is very similar to Sunrise Point for Flashrom's purposes, however one important difference is the way the "number of masters" is interpreted from the flash descriptor (0-based vs. 1-based). There are also new flash regions defined. Change-Id: I96c89bc28bdfcd953229c17679f2c28f8b874d0b Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/20922 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Include <sys/types.h> wherever ssize_t is usedNico Huber2017-08-161-0/+1
| | | | | | | | | | | | `ssize_t` is a POSIX type (cf. IEEE Std 1003.1). Change-Id: I5f6f114523f541b3a8d845c6faee2c0b9f753bae Signed-off-by: Nico Huber <nico.h@gmx.de> Reported-by: Urja Rannikko <urjaman@gmail.com> Reviewed-on: https://review.coreboot.org/21015 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Urja Rannikko <urjaman@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ich_descriptors: Pretty print an assumed chipsetNico Huber2017-07-281-1/+18
| | | | | | | | | | | Change-Id: Id28cb3abc45c6e7f4c4accfc019579c7448c45d7 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20247 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ich_descriptors: Update for Intel SkylakeNico Huber2017-07-281-94/+188
| | | | | | | | | | | | | | | | | | | | | | | Interpretation of component clocks changed. Also more regions and more masters are supported now. The number of regions (NR) is now static per chipset (10 in the 100 Series case) and not coded into the descriptor any more. v2: o Use guess_ich_chipset() for read_ich_descriptors_from_dump(). o Update region extraction in `ich_descriptors_tool`. TEST=Run `ich_descriptors_tool` over a 100 Series dump and checked that output looks sane. Run `ich_descriptors_tool` over dumps of five different older systems (1 x Sandy Bridge, 3 x Ivy Bridge, 1 x Haswell). Beside whitespace changes, regions not accounted by `NR` are not printed any more. Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18973 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ich_descriptors: Add function to guess chipset versionNico Huber2017-07-281-0/+62
| | | | | | | | | | | | | | | | | Add guess_ich_chipset() that takes fields from a descriptor dump and returns the lowest possible chipset version. Intel did several incompatible changes to the descriptor through the years. However, they forgot to add a version number. So we have to apply some heuristics to detect the chipset version in case of exter- nal flashing. Change-Id: Ie1736663dc33801b19d3e695c072c61a6c6345a2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20246 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ich_descriptors: Draw +0xfff into ICH_FREG_LIMIT()Nico Huber2017-07-281-2/+2
| | | | | | | | | | | The condition `base > limit` is still valid since `base` is always at least 4096 greater than `limit` in this case. Change-Id: I11ac0a50b3f32f47879e7cfb7a26068cd0572ede Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19046 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi: Add support for Intel SkylakeNico Huber2017-07-281-15/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Sunrise Point PCH, paired with Skylake, has some minor changes in the HW sequencing interface: * Support for more flash regions moved PR* registers * Only 4KiB erase blocks are supported by the primary erase command * A second erase command for 64KiB pages was added * More commands were added for status register access etc. * A "Dedicated Lock Bits" register was added No support for the new commands was added. The SW sequencing interface seems to have moved register location and is not supported any more officially. It's also untested. Changes are loosely based on the Skylake support commit in Chromium OS by Ramya Vijaykumar: commit a9a64f9e4d52c39fcd3c5f7d7b88065baed189b1 Author: Ramya Vijaykumar <ramya.vijaykumar@intel.com> flashrom: Add Skylake platform support Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
* fixup! Make read_ich_descriptors_from_dump() available in flashromNico Huber2017-06-201-0/+3
| | | | | | | | | | | | | Add a guard around read_ich_descriptors_via_fdo() which uses raw hardware access and is only called from `ichspi`. Fixes linking in case `NEED_RAW_ACCESS != 1`. Change-Id: I5a35c607df44cdbcbacb960f8922c1bf9f1f2002 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20265 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Handle Intel Wildcat Point *LP* like Lynx Point LPNico Huber2017-06-201-1/+4
| | | | | | | | | | | | | | | | | | | | | | | The subtle difference was ignored when adding these chipsets. The integrated Wildcat Point LP PCH is documented in [1]. I'm not sure how to account for "Broadwell H" which seems not publicly documented. Maybe it's an unreleased HM9*, in which case the non-LP path should be correct. [1] Mobile 5th Generation Intel® Core(TM) Processor Family I/O, Intel® Core(TM) M Processor Family I/O, Mobile Intel® Pentium® Processor Family I/O, and Mobile Intel® Celeron® Processor Family I/O Datasheet Revision 004 Document Number: 330837 Change-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18883 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ich_descriptors: Fix more odd +1sNico Huber2017-06-201-9/+7
| | | | | | | | | | | | | | +1 on everything doesn't make software greater per se. v2: o Fix another +1. o Amend style of similar (not +1 suffering) code, too. Change-Id: Ifa5455c999e90ff9121aed29f542d71ac9ca2b1c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Add option to read ROM layout from IFDNico Huber2017-06-141-1/+40
| | | | | | | | | | | | | | | | | | | | | | | | | Add an option --ifd to read the ROM layout from an Intel Firmware Descriptor (IFD). Works the same as the -l option, if given, -i specifies the images to update. v2: o Rebased on libflashrom, use libflashrom interface. o Use functions from ich_descriptors.c. v3: o Move ich_descriptors.o to LIB_OBJS, thus build it independent of arch and programmers. o Bail out if we aren't compiled for little endian. o Update flashrom.8.tmpl. v4: o Incorporated David's comments. o Removed single-character `-d` option. v5: Changed region names to match the output of `ifdtool --layout ...` Change-Id: Ifafff2bf6d5c5e62283416b3269723f81fdc0fa3 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-21 21:36:48 +0000