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* Introduce an `include` directory for header filesThomas Heijligen2022-04-291-595/+0
| | | | | | | | | | | | Move all header files to the new `include` directory. Adapt include directives and build systems to the new directory. Change-Id: Iaddd6bbfa0624b166d422f665877f096983bf4cf Signed-off-by: Felix Singer <felix.singer@secunet.com> Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* Add Tiger Lake U Premium supportMichał Żygowski2021-11-171-0/+7
| | | | | | | | | | | | | | | | | | | | | | Tiger Lake has very low ICCRIBA (TGL=0x11, CNL=0x34 and CML=0x34) and detects as unknown chipset compatible with 300 series chipset. Add a new enum CHIPSET_500_SERIES_TIGER_POINT and treat it identically to CHIPSET_400_SERIES_COMET_POINT. There are some exceptions though, ICCRIBA is no longer present n descriptor content so a new union has been defined for new fields and used in descriptor guessing. freq_read field is not present on Tiger Lake, moreover in CannonPoint and Comet Point this field is used as eSPI/EC frequency, so a new function to print read frequency has ben added. Finally Tiger lake boot straps include eSPI, so a new bus has been added for the new straps. TEST=Flash BIOS region on Intel i5-1135G7 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I28f3b6fe9f8ce9e976a6808683f46b6f4ec72bdd Reviewed-on: https://review.coreboot.org/c/flashrom/+/55578 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ich_descriptors: Revise detection for chipsets w/ ICCRIBANico Huber2021-06-301-1/+2
| | | | | | | | | | | | | | | Detection based on ICCRIBA and FMSBA became a little messy lately. However, there's a new static difference: Since 300 series (Cannon Point), there is an MDTBA field in FLUMAP1 that has always been 0 (reserved) before. Taking this into account, we can relax the checks on ICCRIBA. Change-Id: I587ad1abe390843d4a9e74431b6fc4b63f8ba512 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* layout: Introduce flashrom_layout_new()Nico Huber2021-06-261-6/+1
| | | | | | | | | | | | | | | | | It initializes an empty layout. Currently the maximum number of entries has to be specified, which will vanish once we use dynamic allocation per entry. We replace the two special cases `single_layout` and `ich_layout` with dynamically allocated layouts. As a result, we have to take care to release the `default_layout` in a flashctx once we are done with it. Change-Id: I2ae7246493ff592e631cce924777925c7825e398 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Add Gemini Lake supportAngel Pons2021-05-161-1/+1
| | | | | | | | | | | The SPI hardware is pretty much unchanged from Apollo Lake. However, the IFD differs significantly enough to require special handling. Signed-off-by: Angel Pons <th3fanbus@gmail.com> Change-Id: Ib5dcdf204166f44a8531c19b5f363b851d2ccd77 Reviewed-on: https://review.coreboot.org/c/flashrom/+/54276 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi: Add support for discrete Cannon Lake PCHsNico Huber2019-08-081-4/+6
| | | | | | | | | | | | | | | | Only minor differences in the Firmware Descriptor, compared to their predecessors. We extend our check on the `ICCRIBA` field in the descriptor to dis- tinguish it from older generation. Alas, the `freq_read` field was repurposed, so we can't use it as sanity check any more. Change-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* Remove unneeded white spacesElyes HAOUAS2018-06-241-1/+1
| | | | | | | | | Change-Id: I90f171924790ced74a62ca344fee8607607aa480 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Remove address from GPLv2 headersElyes HAOUAS2018-04-241-4/+0
| | | | | | | | Change-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ich_descriptors: Use MAX_NUM_FLREGS for entries[]David Hendricks2017-09-031-1/+1
| | | | | | | | | | | | 5 regions made sense in 2013 when this bit of code was originally written. MAX_NUM_FLREGS is now used to keep track of the max number of flash regions and is >5 since Sunrise Point. Change-Id: Idb559e618369fecf930724a7c1c84765247f3e38 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/21338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Move ich_layout from layout.h to ich_descriptors.hDavid Hendricks2017-09-031-0/+5
| | | | | | | | | | | | | This moves the ich_layout declaration from one header to another. This will avoid a circular dependency when we update the entries[] member in the follow-up patch to use MAX_NUM_FLREGS which is defined in ich_descriptors.h. Change-Id: I08006f1f7c9ccdd17a9a6d74881ed2c8541d4de1 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/21337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Include <sys/types.h> wherever ssize_t is usedNico Huber2017-08-161-0/+1
| | | | | | | | | | | | `ssize_t` is a POSIX type (cf. IEEE Std 1003.1). Change-Id: I5f6f114523f541b3a8d845c6faee2c0b9f753bae Signed-off-by: Nico Huber <nico.h@gmx.de> Reported-by: Urja Rannikko <urjaman@gmail.com> Reviewed-on: https://review.coreboot.org/21015 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Urja Rannikko <urjaman@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ich_descriptors: Modify limits for C620/Lewisburg PCHDavid Hendricks2017-08-131-2/+3
| | | | | | | | | Change-Id: Ic8adc4b87993e65096166fa6d665432697070b4c Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/20936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ich_descriptors: Pretty print an assumed chipsetNico Huber2017-07-281-0/+1
| | | | | | | | | | | Change-Id: Id28cb3abc45c6e7f4c4accfc019579c7448c45d7 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20247 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ich_descriptors: Update for Intel SkylakeNico Huber2017-07-281-52/+46
| | | | | | | | | | | | | | | | | | | | | | | Interpretation of component clocks changed. Also more regions and more masters are supported now. The number of regions (NR) is now static per chipset (10 in the 100 Series case) and not coded into the descriptor any more. v2: o Use guess_ich_chipset() for read_ich_descriptors_from_dump(). o Update region extraction in `ich_descriptors_tool`. TEST=Run `ich_descriptors_tool` over a 100 Series dump and checked that output looks sane. Run `ich_descriptors_tool` over dumps of five different older systems (1 x Sandy Bridge, 3 x Ivy Bridge, 1 x Haswell). Beside whitespace changes, regions not accounted by `NR` are not printed any more. Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18973 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ich_descriptors: Add function to guess chipset versionNico Huber2017-07-281-3/+4
| | | | | | | | | | | | | | | | | Add guess_ich_chipset() that takes fields from a descriptor dump and returns the lowest possible chipset version. Intel did several incompatible changes to the descriptor through the years. However, they forgot to add a version number. So we have to apply some heuristics to detect the chipset version in case of exter- nal flashing. Change-Id: Ie1736663dc33801b19d3e695c072c61a6c6345a2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20246 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ich_descriptors: Draw +0xfff into ICH_FREG_LIMIT()Nico Huber2017-07-281-1/+1
| | | | | | | | | | | The condition `base > limit` is still valid since `base` is always at least 4096 greater than `limit` in this case. Change-Id: I11ac0a50b3f32f47879e7cfb7a26068cd0572ede Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19046 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi: Add support for Intel SkylakeNico Huber2017-07-281-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Sunrise Point PCH, paired with Skylake, has some minor changes in the HW sequencing interface: * Support for more flash regions moved PR* registers * Only 4KiB erase blocks are supported by the primary erase command * A second erase command for 64KiB pages was added * More commands were added for status register access etc. * A "Dedicated Lock Bits" register was added No support for the new commands was added. The SW sequencing interface seems to have moved register location and is not supported any more officially. It's also untested. Changes are loosely based on the Skylake support commit in Chromium OS by Ramya Vijaykumar: commit a9a64f9e4d52c39fcd3c5f7d7b88065baed189b1 Author: Ramya Vijaykumar <ramya.vijaykumar@intel.com> flashrom: Add Skylake platform support Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
* Add option to read ROM layout from IFDNico Huber2017-06-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Add an option --ifd to read the ROM layout from an Intel Firmware Descriptor (IFD). Works the same as the -l option, if given, -i specifies the images to update. v2: o Rebased on libflashrom, use libflashrom interface. o Use functions from ich_descriptors.c. v3: o Move ich_descriptors.o to LIB_OBJS, thus build it independent of arch and programmers. o Bail out if we aren't compiled for little endian. o Update flashrom.8.tmpl. v4: o Incorporated David's comments. o Removed single-character `-d` option. v5: Changed region names to match the output of `ifdtool --layout ...` Change-Id: Ifafff2bf6d5c5e62283416b3269723f81fdc0fa3 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Make read_ich_descriptors_from_dump() available in flashromNico Huber2017-06-141-11/+0
| | | | | | | | | | | | | | | | | I didn't really know what I was doing and hope removing the #ifdefs doesn't have negative side effects. The idea is to make the functions generally available for external flashing (e.g. you might want to flash an Intel machine using an ARM device as programmer). Beware of big endian trouble, I guess. :-P Change-Id: Ib3d38a622a581afee87b49777e775942cc901fc8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Fix wrong density encoding on Intel SilvermontTai-Hong Wu2015-01-051-11/+7
| | | | | | | | | | | | | | Silvermont (Bay Trail, Rangeley, Avoton) seems to still use the old density encoding with 3 bits per chip. Documentation is unavailable (held concealed by Intel) but thanks to the efforts of Tai-Hong (Type) Wu the layout is clear now. This patch is based on his one but solves the issue differently thus reducing the code complexity. Corresponding to flashrom svn r1861. Signed-off-by: Tai-Hong Wu <thwu@lunartoday.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for Intel Wildcat Point PCHDuncan Laurie2014-08-201-1/+1
| | | | | | | | | | | The Wildcat Point PCH can be paired with Broadwell or Haswell. This patch was essentially backported from ChromiumOS commit 9bd2af8. Corresponding to flashrom svn r1845. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Refine Flash Component descriptor handlingStefan Tauner2014-08-201-7/+34
| | | | | | | | | | | | | | | Possible values as well as encodings have changed in newer chipsets as follows. - Pre-PCH (i.e. ICH) chipsets had a maximum frequency of 33 MHz for all operations - Since Cougar Point the chipsets support dual output fast reads (encoded in bit 30). - Flash component density encoding has changed from 3 to 4 bits with Lynx Point, currently allowing for up to 64 MB chips. Corresponding to flashrom svn r1843. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add a bunch of new/tested stuff and various small changes 13Stefan Tauner2012-07-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested Mainboards: OK: - ASRock A780FullHD http://www.flashrom.org/pipermail/flashrom/2012-July/009599.html - ASRock 880G Pro3 http://www.flashrom.org/pipermail/flashrom/2012-July/009492.html - ASRock N61P-S http://www.flashrom.org/pipermail/flashrom/2012-May/009316.html - ASUS M2N68-VM http://www.flashrom.org/pipermail/flashrom/2012-May/009334.html - ASUS M3N78 PRO http://www.flashrom.org/pipermail/flashrom/2012-July/009519.html - ASUS M4N68T V2 http://www.flashrom.org/pipermail/flashrom/2012-May/009277.html - ASUS M5A78L-M LX reported by clavile on IRC - ASUS P8P67 PRO (rev. 3.0) http://www.flashrom.org/pipermail/flashrom/2012-April/009188.html - ASUS P8Z68-V reported by Kano on IRC http://paste.flashrom.org/view.php?id=1232 - ASUS SABERTOOTH 990FX http://paste.flashrom.org/view.php?id=1214 - Dell Inspiron 1420 http://www.flashrom.org/pipermail/flashrom/2012-May/009196.html - ECS GF8200A http://www.flashrom.org/pipermail/flashrom/2012-May/009256.html - GIGABYTE GA-H61M-D2H-USB3 http://www.flashrom.org/pipermail/flashrom/2012-May/009333.html - MSI MS-7250 (K9N SLI (rev 2.1)) http://www.flashrom.org/pipermail/flashrom/2012-June/009436.html - MSI MS-7676 (Z68MA-G45 (B3)) http://www.flashrom.org/pipermail/flashrom/2012-June/009424.html - Palit N61S http://www.flashrom.org/pipermail/flashrom/2012-May/009212.html NOT OK: - ASRock H61M-ITX http://www.flashrom.org/pipermail/flashrom/2012-May/009224.html - Dell Latitude E6520 http://www.flashrom.org/pipermail/flashrom/2012-May/009197.html - Dell Vostro 3700 http://www.flashrom.org/pipermail/flashrom/2012-May/009197.html - Intel DH61AG http://www.flashrom.org/pipermail/flashrom/2012-June/009417.html - Intel DQ965GF http://www.flashrom.org/pipermail/flashrom/2012-May/009295.html - HP/Compaq 8100 Elite CMT PC (304Bh) http://paste.flashrom.org/view.php?id=1182 - HP Z400 Workstation (0AE4h) http://www.flashrom.org/pipermail/flashrom/2012-June/009350.html - Supermicro X9DR3-F http://www.flashrom.org/pipermail/flashrom/2012-June/009422.html Tested flash chips: - mark AMIC A25L032 as TEST_OK_PREW (+PREW) http://www.flashrom.org/pipermail/flashrom/2012-June/009363.html - mark Atmel AT25DF321A as TEST_OK_PREW (+REW) http://www.flashrom.org/pipermail/flashrom/2012-July/009492.html - mark Atmel AT26DF161 as TEST_OK_PR (+PR) http://www.flashrom.org/pipermail/flashrom/2012-June/009350.html - mark Eon EN25QH16 as TEST_OK_PR (+PR) http://www.flashrom.org/pipermail/flashrom/2012-July/009566.html - mark SST SST39VF010 as TEST_OK_PREW (+W) http://www.flashrom.org/pipermail/flashrom/2012-June/009425.html - mark ST M25P64 as TEST_OK_PREW (+PREW) http://www.flashrom.org/pipermail/flashrom/2012-May/009332.html Tested chipset enables: - Intel 3420 http://www.flashrom.org/pipermail/flashrom/2012-May/009332.html - Add board enable for ASUS P5GD2-X lspci: http://paste.flashrom.org/view.php?id=1234 write: http://paste.flashrom.org/view.php?id=1240 Miscellaneous - Reorder some boards in print.c. - Remove broken abit URLs. - Whitespace changes. - Fix the maximum number of southbridge straps in the ICH descriptor structs. - Refine documentation regarding ICH region lock bits. - Demote verbosity of ICH Opcode reprogramming to -VV. - Exclude Pony-SPI for DOS targets (missing serial support). Corresponding to flashrom svn r1554. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add ich_descriptor_tool to decode all flash descriptors stored in a flash ↵Stefan Tauner2011-12-241-1/+328
| | | | | | | | | | | | | | | | | | | | | | | | | | | | dump file This patch adds an external utility that shares most of the existing descriptor decoding source code. Additionally to what is available via FDOC/FDOD this allows to access: - the softstraps which are used to configure the chipset by flash content without the need for BIOS routines. on ICH8 it is possible to read those with FDOC/FDOC too, but this was removed in later chipsets. - the ME VSCC (Vendor Specific Component Capabilities) table. simply put, this is an SPI chip database used to figure out the flash's capabilities. - the MAC address stored in the GbE image. Intel thinks this information should be confidential for ICH9 and up, but references some tidbits in their public documentation. This patch includes the human-readable information for ICH8, Ibex Peak (5 series) and Cougar Point (6 series); the latter two were obtained from leaked "SPI Flash Programming Guides" found by google. Data regarding ICH9 and 10 is unknown to us yet. It can probably found in: "Intel® ICH7, ICH8, ICH9 and ICH10 — SPI Family Flash Programming Guide" Information regarding the upcoming Panther Point chipset is also not included. Corresponding to flashrom svn r1480. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Matthias Wenzel <bios@mazzoo.de>
* ichspi: use a variable to distinguish ich generations instead of ↵Stefan Tauner2011-11-061-14/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | spi_programmer->type The type member is enough most of the time to derive the wanted information, but - not always (e.g. ich_set_bbar), - only available after registration, which we want to delay till the end of init, and - we really want to distinguish between chipset version-grained attributes which are not reflected by the registered programmer. Hence this patch introduces a new static variable which is set up early by the init functions and allows us to get rid of all "switch (spi_programmer->type)" in ichspi.c. We reuse the enum introduced for descriptor mode for the type of the new variable. Previously magic numbers were passed by chipset_enable wrappers. Now they use the enumeration items too. To get this working the enum definition had to be moved to programmer.h. Another noteworthy detail: previously we have checked for a valid programmer/ich generation all over the place. I have removed those checks and added one single check in the init method. Calling any function of a programmer without executing the init method first, is undefined behavior. Corresponding to flashrom svn r1460. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* ichspi: add (partially) dead support code for Intel Hardware SequencingStefan Tauner2011-10-201-0/+1
| | | | | | | | | | This was done to ease the review. Another patch will hook up (and explain) this code later. Corresponding to flashrom svn r1452. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* ichspi: add ICH/PCH flash descriptor decoding via FDOC/FDODStefan Tauner2011-09-151-0/+260
Based on the work of Matthias 'mazzoo' Wenzel this patch adds pretty printing of those ICH/PCH flash descriptor sections that are cached/mapped by the chipset (and which are therefore reachable via FDOC/FDOD registers). this includes the following: - content section: describes the image and some generic properties (number of sections, offset of sections, PCH/ICH and MCH/PROC strap offsets and lengths) - component section: identify the different SPI flash chips and their capabilities. - region section similarly to a partition table this describes the different regions. the content of FLREG* is derived from this section. - master section defines SPI master (host, ME, GbE) access rights of the individual regions. the content of PR* is derived from this section. this is only a part of the data included in the descriptor. other information can be retrieved from a complete binary dump of the descriptor region only. this patch also adds macros and pretty printing for "Vendor Specific Component Capabilities" registers: there are two of them: lower and upper. they describe the properties of the address space divided by FPBA (which allows to use multiple flash chips or partitions with different properties). the properties of all supported flash chips (together with their RDIDs) are stored in the same format in table in a descriptor section (which is used by the ME apparently). a later patch will use the macros outside of ichspi.c which is the reason why the prettyprinting function and the register bit macros are not defined in ichspi.c but ich_descriptors.h (else they would be moved in the follow-up patch). because this patch relies on (compiler) implementation-specific layouting of bit-fields, it checks for correct layout before taking any action on runtime. Corresponding to flashrom svn r1443. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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