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| author | Yinbo Zhu <zhuyinbo@loongson.cn> | 2022-11-29 11:41:54 +0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-02-10 15:32:28 -0800 |
| commit | 01d63ce42546db93734949ba1cd44359f7f6ee02 (patch) | |
| tree | d22a65a3c795af1dfde9be1b76e4ed445b21c772 | |
| parent | 1b929c02afd37871d5afb9d498426f83432e71c2 (diff) | |
| download | linux-stable-01d63ce42546db93734949ba1cd44359f7f6ee02.tar.gz linux-stable-01d63ce42546db93734949ba1cd44359f7f6ee02.tar.bz2 linux-stable-01d63ce42546db93734949ba1cd44359f7f6ee02.zip | |
dt-bindings: clock: add loongson-2 clock include file
This file defines all Loongson-2 SoC clock indexes, it should be
included in the device tree in which there's device using the
clocks.
Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221129034157.15036-1-zhuyinbo@loongson.cn
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| -rw-r--r-- | MAINTAINERS | 6 | ||||
| -rw-r--r-- | include/dt-bindings/clock/loongson,ls2k-clk.h | 29 |
2 files changed, 35 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index f61eb221415b..ecb6537bf3e5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12195,6 +12195,12 @@ S: Maintained F: Documentation/devicetree/bindings/pinctrl/loongson,ls2k-pinctrl.yaml F: drivers/pinctrl/pinctrl-loongson2.c +LOONGSON-2 SOC SERIES CLOCK DRIVER +M: Yinbo Zhu <zhuyinbo@loongson.cn> +L: linux-clk@vger.kernel.org +S: Maintained +F: include/dt-bindings/clock/loongson,ls2k-clk.h + LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI) M: Sathya Prakash <sathya.prakash@broadcom.com> M: Sreekanth Reddy <sreekanth.reddy@broadcom.com> diff --git a/include/dt-bindings/clock/loongson,ls2k-clk.h b/include/dt-bindings/clock/loongson,ls2k-clk.h new file mode 100644 index 000000000000..db1e27e792ff --- /dev/null +++ b/include/dt-bindings/clock/loongson,ls2k-clk.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Author: Yinbo Zhu <zhuyinbo@loongson.cn> + * Copyright (C) 2022-2023 Loongson Technology Corporation Limited + */ + +#ifndef __DT_BINDINGS_CLOCK_LOONGSON2_H +#define __DT_BINDINGS_CLOCK_LOONGSON2_H + +#define LOONGSON2_REF_100M 0 +#define LOONGSON2_NODE_PLL 1 +#define LOONGSON2_DDR_PLL 2 +#define LOONGSON2_DC_PLL 3 +#define LOONGSON2_PIX0_PLL 4 +#define LOONGSON2_PIX1_PLL 5 +#define LOONGSON2_NODE_CLK 6 +#define LOONGSON2_HDA_CLK 7 +#define LOONGSON2_GPU_CLK 8 +#define LOONGSON2_DDR_CLK 9 +#define LOONGSON2_GMAC_CLK 10 +#define LOONGSON2_DC_CLK 11 +#define LOONGSON2_APB_CLK 12 +#define LOONGSON2_USB_CLK 13 +#define LOONGSON2_SATA_CLK 14 +#define LOONGSON2_PIX0_CLK 15 +#define LOONGSON2_PIX1_CLK 16 +#define LOONGSON2_CLK_END 17 + +#endif |