diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2020-05-08 11:59:18 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-05-20 08:18:53 +0200 |
| commit | 1c87f4f38d73a9ef33972fd4b6ae15f19e0d7398 (patch) | |
| tree | f7e3d0a923fb66c1f0823a3876bc1a3f53c828bc | |
| parent | 48ca4ccf02759b7ae8dea4d916cd91a703e2931d (diff) | |
| download | linux-stable-1c87f4f38d73a9ef33972fd4b6ae15f19e0d7398.tar.gz linux-stable-1c87f4f38d73a9ef33972fd4b6ae15f19e0d7398.tar.bz2 linux-stable-1c87f4f38d73a9ef33972fd4b6ae15f19e0d7398.zip | |
ARM: dts: r8a7740: Add missing extal2 to CPG node
commit e47cb97f153193d4b41ca8d48127da14513d54c7 upstream.
The Clock Pulse Generator (CPG) device node lacks the extal2 clock.
This may lead to a failure registering the "r" clock, or to a wrong
parent for the "usb24s" clock, depending on MD_CK2 pin configuration and
boot loader CPG_USBCKCR register configuration.
This went unnoticed, as this does not affect the single upstream board
configuration, which relies on the first clock input only.
Fixes: d9ffd583bf345e2e ("ARM: shmobile: r8a7740: add SoC clocks to DTS")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20200508095918.6061-1-geert+renesas@glider.be
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | arch/arm/boot/dts/r8a7740.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 383cba68dbba..e12ea97eae27 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -479,7 +479,7 @@ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7740-cpg-clocks"; reg = <0xe6150000 0x10000>; - clocks = <&extal1_clk>, <&extalr_clk>; + clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>; #clock-cells = <1>; clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r", |