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authorWenjing Liu <Wenjing.Liu@amd.com>2017-08-23 17:02:34 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-09-26 18:17:08 -0400
commit1cf49dea28dfc76f0816a4bc73c2ab975c72f55d (patch)
treeb10986b0a1c45c80194fdf703eb2a07cd058176d
parent156590454259a19d1709fab2ff7d59870574e822 (diff)
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drm/amd/display: do not reset lane count in EQ fallback
[Description] According to DP1.4 specs we should not reset lane count back when falling back in failing EQ training. This causes PHY test pattern compliance to fail as infinite LT when LT fails EQ to 4 RBR and fails CR in a loop. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index e19447d526ea..446e2933474c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1302,8 +1302,6 @@ bool decide_fallback_link_setting(
current_link_setting->lane_count);
} else if (!reached_minimum_link_rate
(current_link_setting->link_rate)) {
- current_link_setting->lane_count =
- initial_link_settings.lane_count;
current_link_setting->link_rate =
reduce_link_rate(
current_link_setting->link_rate);