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authorJonathan Cameron <Jonathan.Cameron@huawei.com>2024-04-12 17:10:56 +0100
committerSuzuki K Poulose <suzuki.poulose@arm.com>2024-05-02 11:36:11 +0100
commit1f82d58ddbe21ed75c04d04403d8268a95e0190a (patch)
tree6ddada3d22c4600f6bdf64d30949622f708c33cb
parent8877ef45ef9ec281849870d88039f8dc84cde774 (diff)
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Documentation: ABI + trace: hisi_ptt: update paths to bus/event_source
To allow for assigning a suitable parent to the struct pmu device update the documentation to describe the device via the event_source bus where it will remain accessible. For the ABI documention file also rename the file as it is named after the path. Reviewed-by: Yicong Yang <yangyicong@hisilicon.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20240412161057.14099-30-Jonathan.Cameron@huawei.com
-rw-r--r--Documentation/ABI/testing/sysfs-bus-event_source-devices-hisi_ptt (renamed from Documentation/ABI/testing/sysfs-devices-hisi_ptt)12
-rw-r--r--Documentation/trace/hisi-ptt.rst4
-rw-r--r--MAINTAINERS2
3 files changed, 9 insertions, 9 deletions
diff --git a/Documentation/ABI/testing/sysfs-devices-hisi_ptt b/Documentation/ABI/testing/sysfs-bus-event_source-devices-hisi_ptt
index d7e206b4901c..1119766564d7 100644
--- a/Documentation/ABI/testing/sysfs-devices-hisi_ptt
+++ b/Documentation/ABI/testing/sysfs-bus-event_source-devices-hisi_ptt
@@ -1,4 +1,4 @@
-What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune
+What: /sys/bus/event_source/devices/hisi_ptt<sicl_id>_<core_id>/tune
Date: October 2022
KernelVersion: 6.1
Contact: Yicong Yang <yangyicong@hisilicon.com>
@@ -8,7 +8,7 @@ Description: This directory contains files for tuning the PCIe link
See Documentation/trace/hisi-ptt.rst for more information.
-What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_cpl
+What: /sys/bus/event_source/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_cpl
Date: October 2022
KernelVersion: 6.1
Contact: Yicong Yang <yangyicong@hisilicon.com>
@@ -18,7 +18,7 @@ Description: (RW) Controls the weight of Tx completion TLPs, which influence
will return an error, and out of range values will be converted
to 2. The value indicates a probable level of the event.
-What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_np
+What: /sys/bus/event_source/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_np
Date: October 2022
KernelVersion: 6.1
Contact: Yicong Yang <yangyicong@hisilicon.com>
@@ -28,7 +28,7 @@ Description: (RW) Controls the weight of Tx non-posted TLPs, which influence
will return an error, and out of range values will be converted
to 2. The value indicates a probable level of the event.
-What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_p
+What: /sys/bus/event_source/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_p
Date: October 2022
KernelVersion: 6.1
Contact: Yicong Yang <yangyicong@hisilicon.com>
@@ -38,7 +38,7 @@ Description: (RW) Controls the weight of Tx posted TLPs, which influence the
will return an error, and out of range values will be converted
to 2. The value indicates a probable level of the event.
-What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/rx_alloc_buf_level
+What: /sys/bus/event_source/devices/hisi_ptt<sicl_id>_<core_id>/tune/rx_alloc_buf_level
Date: October 2022
KernelVersion: 6.1
Contact: Yicong Yang <yangyicong@hisilicon.com>
@@ -49,7 +49,7 @@ Description: (RW) Control the allocated buffer watermark for inbound packets.
will return an error, and out of range values will be converted
to 2. The value indicates a probable level of the event.
-What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/tx_alloc_buf_level
+What: /sys/bus/event_source/devices/hisi_ptt<sicl_id>_<core_id>/tune/tx_alloc_buf_level
Date: October 2022
KernelVersion: 6.1
Contact: Yicong Yang <yangyicong@hisilicon.com>
diff --git a/Documentation/trace/hisi-ptt.rst b/Documentation/trace/hisi-ptt.rst
index 989255eb5622..6eef28ebb0c7 100644
--- a/Documentation/trace/hisi-ptt.rst
+++ b/Documentation/trace/hisi-ptt.rst
@@ -40,7 +40,7 @@ IO dies (SICL, Super I/O Cluster), where there's one PCIe Root
Complex for each SICL.
::
- /sys/devices/hisi_ptt<sicl_id>_<core_id>
+ /sys/bus/event_source/devices/hisi_ptt<sicl_id>_<core_id>
Tune
====
@@ -53,7 +53,7 @@ Each event is presented as a file under $(PTT PMU dir)/tune, and
a simple open/read/write/close cycle will be used to tune the event.
::
- $ cd /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune
+ $ cd /sys/bus/event_source/devices/hisi_ptt<sicl_id>_<core_id>/tune
$ ls
qos_tx_cpl qos_tx_np qos_tx_p
tx_path_rx_req_alloc_buf_level
diff --git a/MAINTAINERS b/MAINTAINERS
index c23fda1aa1f0..63a55f1559f4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9790,7 +9790,7 @@ M: Yicong Yang <yangyicong@hisilicon.com>
M: Jonathan Cameron <jonathan.cameron@huawei.com>
L: linux-kernel@vger.kernel.org
S: Maintained
-F: Documentation/ABI/testing/sysfs-devices-hisi_ptt
+F: Documentation/ABI/testing/sysfs-bus-event_source-devices-hisi_ptt
F: Documentation/trace/hisi-ptt.rst
F: drivers/hwtracing/ptt/
F: tools/perf/arch/arm64/util/hisi-ptt.c