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author | Florian Fainelli <f.fainelli@gmail.com> | 2020-07-09 15:30:16 -0700 |
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committer | Marc Zyngier <maz@kernel.org> | 2020-07-17 13:41:42 +0100 |
commit | 240e176a96187ee84e63626ca0d1aac92da503aa (patch) | |
tree | 3de8966543a9d32cf48c8853674af4479c4db84d | |
parent | 03a7ac47c14c7ef50742a34b3cfba1a47a578a03 (diff) | |
download | linux-stable-240e176a96187ee84e63626ca0d1aac92da503aa.tar.gz linux-stable-240e176a96187ee84e63626ca0d1aac92da503aa.tar.bz2 linux-stable-240e176a96187ee84e63626ca0d1aac92da503aa.zip |
irqchip/brcmstb-l2: Match UPG_AUX_AON_INTR2 compatible
The UPG_AUX_AON_INTR2 Level 2 interrupt controller node is defined with
the "brcm,upg-aux-aon-l2-intc" compatible string in Device Tree and
behaves as an edge triggered standard Broadcom STB L2 interrupt
controller.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200709223016.989-7-f.fainelli@gmail.com
-rw-r--r-- | drivers/irqchip/irq-brcmstb-l2.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/irqchip/irq-brcmstb-l2.c b/drivers/irqchip/irq-brcmstb-l2.c index b10fe5042a2f..cdd6a42d4efa 100644 --- a/drivers/irqchip/irq-brcmstb-l2.c +++ b/drivers/irqchip/irq-brcmstb-l2.c @@ -278,6 +278,8 @@ static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np, IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_edge_intc_of_init); IRQCHIP_DECLARE(brcmstb_hif_spi_l2_intc, "brcm,hif-spi-l2-intc", brcmstb_l2_edge_intc_of_init); +IRQCHIP_DECLARE(brcmstb_upg_aux_aon_l2_intc, "brcm,upg-aux-aon-l2-intc", + brcmstb_l2_edge_intc_of_init); static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np, struct device_node *parent) |