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authorFabio Estevam <festevam@gmail.com>2019-06-14 15:32:20 +0100
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2019-06-19 19:35:51 +0200
commit2d1c193911b03b77b2f4df8df07578af43ce5564 (patch)
treedc7fba4c1126f4c56fe0ab621d04e8dcc8af8860
parent67ff708bd2facd0a7b93f3c5960586999962456d (diff)
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nvmem: Broaden the selection of NVMEM_SNVS_LPGPR
The SNVS LPGR IP block is also found on other i.MX SoCs that are not covered by the current SOC_IMX6 || SOC_IMX7D logic. One example is the i.MX7ULP. To avoid keep expanding the SoC logic selection, make it broader by using the more generic ARCH_MXC symbol instead. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/nvmem/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index d2b0374dff80..c2ec750cae6e 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -195,7 +195,7 @@ config MESON_MX_EFUSE
config NVMEM_SNVS_LPGPR
tristate "Support for Low Power General Purpose Register"
- depends on SOC_IMX6 || SOC_IMX7D || COMPILE_TEST
+ depends on ARCH_MXC || COMPILE_TEST
help
This is a driver for Low Power General Purpose Register (LPGPR) available on
i.MX6 and i.MX7 SoCs in Secure Non-Volatile Storage (SNVS) of this chip.