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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2023-07-14 08:56:49 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-07-25 11:12:28 +0200 |
| commit | 2fd3f06b527e6ffaa929129a267386961e20a86c (patch) | |
| tree | 69550c1804ca9158669e15426282554cda750a8a | |
| parent | bbceb13ce2c7b084bbbf2463ac8ac2b1f2bd2949 (diff) | |
| download | linux-stable-2fd3f06b527e6ffaa929129a267386961e20a86c.tar.gz linux-stable-2fd3f06b527e6ffaa929129a267386961e20a86c.tar.bz2 linux-stable-2fd3f06b527e6ffaa929129a267386961e20a86c.zip | |
clk: renesas: r9a07g043: Add MTU3a clock and reset entry
Add MTU3a clock and reset entry to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230714075649.146978-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | drivers/clk/renesas/r9a07g043-cpg.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 99f72bf590fa..1a7a6d60aca4 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -154,6 +154,8 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x534, 1), DEF_MOD("ostm2_pclk", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0, 0x534, 2), + DEF_MOD("mtu_x_mck", R9A07G043_MTU_X_MCK_MTU3, R9A07G043_CLK_P0, + 0x538, 0), DEF_MOD("wdt0_pclk", R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0, 0x548, 0), DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK, @@ -264,6 +266,7 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0), DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1), DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2), + DEF_RST(R9A07G043_MTU_X_PRESET_MTU3, 0x838, 0), DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0), DEF_RST(R9A07G043_SPI_RST, 0x850, 0), DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0), |