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authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>2022-05-06 18:21:04 +0300
committerBjorn Andersson <andersson@kernel.org>2022-08-29 15:14:16 -0500
commit3e4fec3bc8f8d1366cf2d8d8a054ed37e5a41cba (patch)
tree0c78a1d54bcc627bceea3ae9c617edd3c8de04fc
parentca1ce7207e53cfe69aee5002eb3795069668da53 (diff)
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arm64: dts: qcom: stop using snps,dw-pcie falback
Qualcomm PCIe devices are not really compatible with the snps,dw-pcie. Unlike the generic IP core, they have special requirements regarding enabling clocks, toggling resets, using the PHY, etc. This is not to mention that platform snps-dw-pcie driver expects to find two IRQs declared, while Qualcomm platforms use just one. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220506152107.1527552-6-dmitry.baryshkov@linaro.org
-rw-r--r--arch/arm64/boot/dts/qcom/qcs404.dtsi2
-rw-r--r--arch/arm64/boot/dts/qcom/sm8250.dtsi6
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 9ab990061522..1881d810a429 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -1297,7 +1297,7 @@
};
pcie: pci@10000000 {
- compatible = "qcom,pcie-qcs404", "snps,dw-pcie";
+ compatible = "qcom,pcie-qcs404";
reg = <0x10000000 0xf1d>,
<0x10000f20 0xa8>,
<0x07780000 0x2000>,
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index bc773e210023..8124f38863e2 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -1792,7 +1792,7 @@
};
pcie0: pci@1c00000 {
- compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
+ compatible = "qcom,pcie-sm8250";
reg = <0 0x01c00000 0 0x3000>,
<0 0x60000000 0 0xf1d>,
<0 0x60000f20 0 0xa8>,
@@ -1893,7 +1893,7 @@
};
pcie1: pci@1c08000 {
- compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
+ compatible = "qcom,pcie-sm8250";
reg = <0 0x01c08000 0 0x3000>,
<0 0x40000000 0 0xf1d>,
<0 0x40000f20 0 0xa8>,
@@ -2001,7 +2001,7 @@
};
pcie2: pci@1c10000 {
- compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
+ compatible = "qcom,pcie-sm8250";
reg = <0 0x01c10000 0 0x3000>,
<0 0x64000000 0 0xf1d>,
<0 0x64000f20 0 0xa8>,