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| author | David Daney <ddaney@caviumnetworks.com> | 2008-12-11 15:33:27 -0800 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2009-01-11 09:57:22 +0000 |
| commit | 47d979eca33f8df49bfead2d5efa23a70b413882 (patch) | |
| tree | e70554c6042ba2acf5c01df8e15a572ebf6e60d3 | |
| parent | 0dd4781bca56871434507ed35d5bb8ef92077907 (diff) | |
| download | linux-stable-47d979eca33f8df49bfead2d5efa23a70b413882.tar.gz linux-stable-47d979eca33f8df49bfead2d5efa23a70b413882.tar.bz2 linux-stable-47d979eca33f8df49bfead2d5efa23a70b413882.zip | |
MIPS: Hook Cavium OCTEON cache init into cache.c
Follow precedent of other boards, and hook-up the CPU specific cache
init.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/include/asm/cpu-features.h | 3 | ||||
| -rw-r--r-- | arch/mips/mm/cache.c | 6 |
2 files changed, 9 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 12d12dfe73c0..a0d14f85b781 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -38,6 +38,9 @@ #ifndef cpu_has_tx39_cache #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) #endif +#ifndef cpu_has_octeon_cache +#define cpu_has_octeon_cache 0 +#endif #ifndef cpu_has_fpu #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) #define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 1eb7c71e3d6a..98ad0a82c29e 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -182,6 +182,12 @@ void __devinit cpu_cache_init(void) tx39_cache_init(); } + if (cpu_has_octeon_cache) { + extern void __weak octeon_cache_init(void); + + octeon_cache_init(); + } + setup_protection_map(); } |