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| author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-04-22 00:31:57 +0200 |
|---|---|---|
| committer | Matthias Brugger <matthias.bgg@gmail.com> | 2023-05-29 17:42:19 +0200 |
| commit | 492061bfc045d815aa5414c1a5eaf373c2fb89fe (patch) | |
| tree | a7db510d040cb8ac4a7c5bd00c986b7ba0efe605 | |
| parent | ea6c5f21efecbaa3a14cb21c5bc0e23c84473a11 (diff) | |
| download | linux-stable-492061bfc045d815aa5414c1a5eaf373c2fb89fe.tar.gz linux-stable-492061bfc045d815aa5414c1a5eaf373c2fb89fe.tar.bz2 linux-stable-492061bfc045d815aa5414c1a5eaf373c2fb89fe.zip | |
arm64: dts: mediatek: add missing cache properties
As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:
mt7622-rfb1.dtb: l2-cache: 'cache-unified' is a required property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230421223157.115367-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8186.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 |
4 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 006cd639059f..36ef2dbe8add 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -101,6 +101,7 @@ L2: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 29dddd8c08f1..8c02232cac38 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -258,6 +258,7 @@ cache-line-size = <64>; cache-sets = <512>; next-level-cache = <&l3_0>; + cache-unified; }; l2_1: l2-cache1 { @@ -267,6 +268,7 @@ cache-line-size = <64>; cache-sets = <512>; next-level-cache = <&l3_0>; + cache-unified; }; l3_0: l3-cache { diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 5c30caf74026..faaff39155dc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -228,6 +228,7 @@ cache-line-size = <64>; cache-sets = <512>; next-level-cache = <&l3_0>; + cache-unified; }; l2_1: l2-cache1 { @@ -237,6 +238,7 @@ cache-line-size = <64>; cache-sets = <512>; next-level-cache = <&l3_0>; + cache-unified; }; l3_0: l3-cache { diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 2cef831d952b..b53e95991199 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -285,6 +285,7 @@ cache-line-size = <64>; cache-sets = <512>; next-level-cache = <&l3_0>; + cache-unified; }; l2_1: l2-cache1 { @@ -294,6 +295,7 @@ cache-line-size = <64>; cache-sets = <512>; next-level-cache = <&l3_0>; + cache-unified; }; l3_0: l3-cache { |