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| author | Felix Fietkau <nbd@nbd.name> | 2018-07-20 13:58:21 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-07-28 07:55:40 +0200 |
| commit | 4c686d73bc3e090c8d8d55a07a1010955dcce9df (patch) | |
| tree | 62e3bb0dd3cad64360b97c98a0721b53438d68f8 | |
| parent | 4168a84223646130203c7b566c27f9a74abef7ea (diff) | |
| download | linux-stable-4c686d73bc3e090c8d8d55a07a1010955dcce9df.tar.gz linux-stable-4c686d73bc3e090c8d8d55a07a1010955dcce9df.tar.bz2 linux-stable-4c686d73bc3e090c8d8d55a07a1010955dcce9df.zip | |
MIPS: ath79: fix register address in ath79_ddr_wb_flush()
commit bc88ad2efd11f29e00a4fd60fcd1887abfe76833 upstream.
ath79_ddr_wb_flush_base has the type void __iomem *, so register offsets
need to be a multiple of 4 in order to access the intended register.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Fixes: 24b0e3e84fbf ("MIPS: ath79: Improve the DDR controller interface")
Patchwork: https://patchwork.linux-mips.org/patch/19912/
Cc: Alban Bedel <albeu@free.fr>
Cc: James Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org # 4.2+
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | arch/mips/ath79/common.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c index 10a405d593df..c782b10ddf50 100644 --- a/arch/mips/ath79/common.c +++ b/arch/mips/ath79/common.c @@ -58,7 +58,7 @@ EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init); void ath79_ddr_wb_flush(u32 reg) { - void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg; + void __iomem *flush_reg = ath79_ddr_wb_flush_base + (reg * 4); /* Flush the DDR write buffer. */ __raw_writel(0x1, flush_reg); |