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authorJudy Hsiao <judyhsiao@chromium.org>2022-04-19 14:29:52 +0800
committerMark Brown <broonie@kernel.org>2022-04-25 14:00:21 +0100
commit4d9596d42152bfd4a57cc317acf9cd0b90769033 (patch)
tree1100fae28e21d4d7ed952032acbf850a059bd219
parent666b0cad75dc9517100295aed590aef2ff9a73d1 (diff)
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ASoC: qcom: Use MCLK as RT5682I-VS sysclk source
Both MCLK and BCLK can be the clock source of sysclk via PLL according to its datasheet. This patch sets MCLK as the clock source as we use MCLK in the previous projects. Fixes: c5198db82d4c ("ASoC: qcom: Add driver support for ALC5682I-VS") Signed-off-by: Judy Hsiao <judyhsiao@chromium.org> Link: https://lore.kernel.org/r/20220419062952.356017-1-judyhsiao@chromium.org Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--sound/soc/qcom/sc7280.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/sound/soc/qcom/sc7280.c b/sound/soc/qcom/sc7280.c
index 4ef4034ba6ee..dfcb7ed44331 100644
--- a/sound/soc/qcom/sc7280.c
+++ b/sound/soc/qcom/sc7280.c
@@ -21,7 +21,7 @@
#include "lpass.h"
#define DEFAULT_MCLK_RATE 19200000
-#define RT5682_PLL1_FREQ (48000 * 512)
+#define RT5682_PLL_FREQ (48000 * 512)
struct sc7280_snd_data {
struct snd_soc_card card;
@@ -137,15 +137,15 @@ static int sc7280_rt5682_init(struct snd_soc_pcm_runtime *rtd)
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_I2S);
- ret = snd_soc_dai_set_pll(codec_dai, RT5682S_PLL1, RT5682S_PLL_S_BCLK1,
- 1536000, RT5682_PLL1_FREQ);
+ ret = snd_soc_dai_set_pll(codec_dai, RT5682S_PLL2, RT5682S_PLL_S_MCLK,
+ DEFAULT_MCLK_RATE, RT5682_PLL_FREQ);
if (ret) {
dev_err(rtd->dev, "can't set codec pll: %d\n", ret);
return ret;
}
- ret = snd_soc_dai_set_sysclk(codec_dai, RT5682S_SCLK_S_PLL1,
- RT5682_PLL1_FREQ,
+ ret = snd_soc_dai_set_sysclk(codec_dai, RT5682S_SCLK_S_PLL2,
+ RT5682_PLL_FREQ,
SND_SOC_CLOCK_IN);
if (ret) {