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| author | Mario Limonciello <mario.limonciello@amd.com> | 2023-12-14 15:07:32 -0600 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-12-19 14:47:15 -0500 |
| commit | 4e08378b2dc1fbe64c9e1730f3260672b22fac03 (patch) | |
| tree | b47cf8147d463f4f59402b7b6595aeb8a7cd8b35 | |
| parent | a0d25fcd75d40441712ff210cba2e49fc771a8b3 (diff) | |
| download | linux-stable-4e08378b2dc1fbe64c9e1730f3260672b22fac03.tar.gz linux-stable-4e08378b2dc1fbe64c9e1730f3260672b22fac03.tar.bz2 linux-stable-4e08378b2dc1fbe64c9e1730f3260672b22fac03.zip | |
drm/amd/display: Add a new DC debug mask for PSR-SU
Some issues have been raised that appear to be tied to PSR-SU.
To allow users to confirm they're tied to PSR-SU without turning off
PSR entirely introduce a new debug mask:
amdgpu.dcdebugmask=0x200
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/amd_shared.h | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c index 08ce3bb8f640..1f08c6564c3b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c @@ -51,6 +51,9 @@ static bool link_supports_psrsu(struct dc_link *link) !link->dpcd_caps.psr_info.psr2_su_y_granularity_cap) return false; + if (amdgpu_dc_debug_mask & DC_DISABLE_PSR_SU) + return false; + return dc_dmub_check_min_version(dc->ctx->dmub_srv->dmub); } diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index bf7f258c324a..c739f12fb937 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -258,6 +258,7 @@ enum DC_DEBUG_MASK { DC_DISABLE_REPLAY = 0x50, DC_ENABLE_DPIA_TRACE = 0x80, DC_ENABLE_DML2 = 0x100, + DC_DISABLE_PSR_SU = 0x200, }; enum amd_dpm_forced_level; |