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| author | Thierry Reding <treding@nvidia.com> | 2014-04-16 09:52:31 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2014-06-05 23:09:19 +0200 |
| commit | 501bcbd1b233edc160d0c770c03747a1c4aa14e5 (patch) | |
| tree | 1c72bbdb41159688d5926fd329af059a70cf0708 | |
| parent | 10288eea885bc32d2c856cd620aeeb83b5f3dd98 (diff) | |
| download | linux-stable-501bcbd1b233edc160d0c770c03747a1c4aa14e5.tar.gz linux-stable-501bcbd1b233edc160d0c770c03747a1c4aa14e5.tar.bz2 linux-stable-501bcbd1b233edc160d0c770c03747a1c4aa14e5.zip | |
drm/tegra: dc - Do not touch power control register
Setting the bits in this register is dependent on the output type driven
by the display controller. All output drivers already set these properly
so there is no need to do it here again.
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | drivers/gpu/drm/tegra/dc.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 8b21e204a3ae..33e03a69a040 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -743,10 +743,6 @@ static void tegra_crtc_prepare(struct drm_crtc *crtc) WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); - value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | - PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; - tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); - /* initialize timer */ value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); |