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| author | Emil Medve <Emilian.Medve@freescale.com> | 2014-11-06 09:48:13 -0600 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2014-11-07 18:10:50 -0600 |
| commit | 58810cb7f66e47fce2e8945deeab5a4226e3975c (patch) | |
| tree | 07213d64f77174360b375c82ae7e479d1669371b | |
| parent | f1aa77c9703148fad7d819d9d764dae0cb82d141 (diff) | |
| download | linux-stable-58810cb7f66e47fce2e8945deeab5a4226e3975c.tar.gz linux-stable-58810cb7f66e47fce2e8945deeab5a4226e3975c.tar.bz2 linux-stable-58810cb7f66e47fce2e8945deeab5a4226e3975c.zip | |
powerpc/dts: Add node(s) for the platform PLL
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Change-Id: If76cd705a01813abe53396c1486bc13c4289ee92
Signed-off-by: Scott Wood <scottwood@freescale.com>
| -rw-r--r-- | arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi | 7 | ||||
| -rw-r--r-- | arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi | 7 |
2 files changed, 14 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi index 48710482806e..4ece1edbff63 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi @@ -75,4 +75,11 @@ global-utilities@e1000 { clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; clock-output-names = "cmux1"; }; + platform_pll: platform-pll@c00 { + #clock-cells = <1>; + reg = <0xc00 0x4>; + compatible = "fsl,qoriq-platform-pll-1.0"; + clocks = <&sysclk>; + clock-output-names = "platform-pll", "platform-pll-div2"; + }; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi index 5d18d2a6cf52..48e0b6e4ce33 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi @@ -58,4 +58,11 @@ global-utilities@e1000 { clocks = <&sysclk>; clock-output-names = "pll1", "pll1-div2", "pll1-div4"; }; + platform_pll: platform-pll@c00 { + #clock-cells = <1>; + reg = <0xc00 0x4>; + compatible = "fsl,qoriq-platform-pll-2.0"; + clocks = <&sysclk>; + clock-output-names = "platform-pll", "platform-pll-div2"; + }; }; |