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| author | Atish Patra <atishp@rivosinc.com> | 2024-08-16 00:08:09 -0700 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2024-08-19 08:58:21 +0530 |
| commit | 5aa09297a3dcc798d038bd7436f8c90f664045a6 (patch) | |
| tree | 49e940c53e6153b0152f481ff13834d83fd0af2b | |
| parent | 7d1ffc8b087e97dbe1985912c7a2d00e53cea169 (diff) | |
| download | linux-stable-5aa09297a3dcc798d038bd7436f8c90f664045a6.tar.gz linux-stable-5aa09297a3dcc798d038bd7436f8c90f664045a6.tar.bz2 linux-stable-5aa09297a3dcc798d038bd7436f8c90f664045a6.zip | |
RISC-V: KVM: Fix to allow hpmcounter31 from the guest
The csr_fun defines a count parameter which defines the total number
CSRs emulated in KVM starting from the base. This value should be
equal to total number of counters possible for trap/emulation (32).
Fixes: a9ac6c37521f ("RISC-V: KVM: Implement trap & emulate for hpmcounters")
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20240816-kvm_pmu_fixes-v1-2-cdfce386dd93@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>
| -rw-r--r-- | arch/riscv/include/asm/kvm_vcpu_pmu.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm/kvm_vcpu_pmu.h index c309daa2d75a..1d85b6617508 100644 --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -65,11 +65,11 @@ struct kvm_pmu { #if defined(CONFIG_32BIT) #define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \ -{.base = CSR_CYCLEH, .count = 31, .func = kvm_riscv_vcpu_pmu_read_hpm }, \ -{.base = CSR_CYCLE, .count = 31, .func = kvm_riscv_vcpu_pmu_read_hpm }, +{.base = CSR_CYCLEH, .count = 32, .func = kvm_riscv_vcpu_pmu_read_hpm }, \ +{.base = CSR_CYCLE, .count = 32, .func = kvm_riscv_vcpu_pmu_read_hpm }, #else #define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \ -{.base = CSR_CYCLE, .count = 31, .func = kvm_riscv_vcpu_pmu_read_hpm }, +{.base = CSR_CYCLE, .count = 32, .func = kvm_riscv_vcpu_pmu_read_hpm }, #endif int kvm_riscv_vcpu_pmu_incr_fw(struct kvm_vcpu *vcpu, unsigned long fid); |