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author | Petr Cvek <petrcvekcz@gmail.com> | 2019-06-20 23:39:37 +0200 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-08-06 19:08:05 +0200 |
commit | 5b14588f001d9cb47ea5a816f00b2efe6f8c1d7e (patch) | |
tree | 27145e595fdd93addc55d653ec31a2241f157796 | |
parent | aaf15ffc6b678c6f9477f672eca7af3165195428 (diff) | |
download | linux-stable-5b14588f001d9cb47ea5a816f00b2efe6f8c1d7e.tar.gz linux-stable-5b14588f001d9cb47ea5a816f00b2efe6f8c1d7e.tar.bz2 linux-stable-5b14588f001d9cb47ea5a816f00b2efe6f8c1d7e.zip |
MIPS: lantiq: Fix bitfield masking
[ Upstream commit ba1bc0fcdeaf3bf583c1517bd2e3e29cf223c969 ]
The modification of EXIN register doesn't clean the bitfield before
the writing of a new value. After a few modifications the bitfield would
accumulate only '1's.
Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: hauke@hauke-m.de
Cc: john@phrozen.org
Cc: linux-mips@vger.kernel.org
Cc: openwrt-devel@lists.openwrt.org
Cc: pakahmar@hotmail.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
-rw-r--r-- | arch/mips/lantiq/irq.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index cfd87e662fcf..9c95097557c7 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -154,8 +154,9 @@ static int ltq_eiu_settype(struct irq_data *d, unsigned int type) if (edge) irq_set_handler(d->hwirq, handle_edge_irq); - ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) | - (val << (i * 4)), LTQ_EIU_EXIN_C); + ltq_eiu_w32((ltq_eiu_r32(LTQ_EIU_EXIN_C) & + (~(7 << (i * 4)))) | (val << (i * 4)), + LTQ_EIU_EXIN_C); } } |