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author | Emil Renner Berthing <emil.renner.berthing@canonical.com> | 2023-11-30 16:19:25 +0100 |
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committer | Conor Dooley <conor.dooley@microchip.com> | 2023-12-13 15:41:59 +0000 |
commit | 64fc984a8a54163a5c44e15a54b574a2c5564d8f (patch) | |
tree | 6488ecea5965483871c4f25a654d19904e8fe0b5 | |
parent | 0d5701dc9cd653ae757cc06e39b3a39272863395 (diff) | |
download | linux-stable-64fc984a8a54163a5c44e15a54b574a2c5564d8f.tar.gz linux-stable-64fc984a8a54163a5c44e15a54b574a2c5564d8f.tar.bz2 linux-stable-64fc984a8a54163a5c44e15a54b574a2c5564d8f.zip |
riscv: errata: Add StarFive JH7100 errata
This not really an errata, but since the JH7100 was made before
the standard Zicbom extension it needs the DMA_GLOBAL_POOL and
RISCV_NONSTANDARD_CACHE_OPS enabled to work correctly.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
-rw-r--r-- | arch/riscv/Kconfig.errata | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index e2c731cfed8c..692de149141f 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -53,6 +53,23 @@ config ERRATA_SIFIVE_CIP_1200 If you don't know what to do here, say "Y". +config ERRATA_STARFIVE_JH7100 + bool "StarFive JH7100 support" + depends on ARCH_STARFIVE && NONPORTABLE + select DMA_GLOBAL_POOL + select RISCV_DMA_NONCOHERENT + select RISCV_NONSTANDARD_CACHE_OPS + select SIFIVE_CCACHE + default n + help + The StarFive JH7100 was a test chip for the JH7110 and has + caches that are non-coherent with respect to peripheral DMAs. + It was designed before the Zicbom extension so needs non-standard + cache operations through the SiFive cache controller. + + Say "Y" if you want to support the BeagleV Starlight and/or + StarFive VisionFive V1 boards. + config ERRATA_THEAD bool "T-HEAD errata" depends on RISCV_ALTERNATIVE |