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| author | Paul Hsieh <Paul.Hsieh@amd.com> | 2022-11-24 13:03:26 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-12-06 10:16:24 -0500 |
| commit | 8747075f54fa0c5d30fcc48e5149c19c02641fa8 (patch) | |
| tree | 48ce7caf8d59d400f16e7e7b3fa0c3092d59644c | |
| parent | 2a2acdd7f84fe97ef9c74dd4da99b67b61a97521 (diff) | |
| download | linux-stable-8747075f54fa0c5d30fcc48e5149c19c02641fa8.tar.gz linux-stable-8747075f54fa0c5d30fcc48e5149c19c02641fa8.tar.bz2 linux-stable-8747075f54fa0c5d30fcc48e5149c19c02641fa8.zip | |
drm/amd/display: read invalid ddc pin status cause engine busy
[Why]
There is no DDC_6 pin on new asic cause the mapping table is
incorrect. When app try to access DDC_VGA port, driver read
an invalid ddc pin status and report engine busy.
[How]
Add dummy DDC_6 pin to align gpio structure.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Paul Hsieh <Paul.Hsieh@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c index 0ea52ba5ac82..9fd8b269dd79 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c @@ -256,8 +256,8 @@ static const struct hw_factory_funcs funcs = { */ void dal_hw_factory_dcn32_init(struct hw_factory *factory) { - factory->number_of_pins[GPIO_ID_DDC_DATA] = 6; - factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 6; + factory->number_of_pins[GPIO_ID_DDC_DATA] = 8; + factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8; factory->number_of_pins[GPIO_ID_GENERIC] = 4; factory->number_of_pins[GPIO_ID_HPD] = 5; factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28; |