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| author | Joey Gouly <joey.gouly@arm.com> | 2023-10-03 13:45:43 +0100 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2023-10-13 19:12:34 +0100 |
| commit | 94d0657f9f0d311489606589133ebf49e28104d8 (patch) | |
| tree | c77db295ea1eb7df914482dcfc6fd6994ed9fff6 | |
| parent | 80652cc0c0485da593c1639a6355dcdab95364e6 (diff) | |
| download | linux-stable-94d0657f9f0d311489606589133ebf49e28104d8.tar.gz linux-stable-94d0657f9f0d311489606589133ebf49e28104d8.tar.bz2 linux-stable-94d0657f9f0d311489606589133ebf49e28104d8.zip | |
arm64: add FEAT_LSE128 HWCAP
Add HWCAP for FEAT_LSE128 (128-bit Atomic instructions).
Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20231003124544.858804-2-joey.gouly@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| -rw-r--r-- | Documentation/arch/arm64/elf_hwcaps.rst | 3 | ||||
| -rw-r--r-- | arch/arm64/include/asm/hwcap.h | 1 | ||||
| -rw-r--r-- | arch/arm64/include/uapi/asm/hwcap.h | 1 | ||||
| -rw-r--r-- | arch/arm64/kernel/cpufeature.c | 1 | ||||
| -rw-r--r-- | arch/arm64/kernel/cpuinfo.c | 1 | ||||
| -rw-r--r-- | arch/arm64/tools/sysreg | 1 |
6 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/arm64/elf_hwcaps.rst index a453f8430f7f..4b8399ac592b 100644 --- a/Documentation/arch/arm64/elf_hwcaps.rst +++ b/Documentation/arch/arm64/elf_hwcaps.rst @@ -314,6 +314,9 @@ HWCAP2_SVE_B16B16 HWCAP2_LRCPC3 Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0011. +HWCAP2_LSE128 + Functionality implied by ID_AA64ISAR0_EL1.Atomic == 0b0011. + 4. Unused AT_HWCAP bits ----------------------- diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index 1c65f10619a0..cd71e09ea14d 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -141,6 +141,7 @@ #define KERNEL_HWCAP_HBC __khwcap2_feature(HBC) #define KERNEL_HWCAP_SVE_B16B16 __khwcap2_feature(SVE_B16B16) #define KERNEL_HWCAP_LRCPC3 __khwcap2_feature(LRCPC3) +#define KERNEL_HWCAP_LSE128 __khwcap2_feature(LSE128) /* * This yields a mask that user programs can use to figure out what diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index 0f37944e98b6..5023599fa278 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -106,5 +106,6 @@ #define HWCAP2_HBC (1UL << 44) #define HWCAP2_SVE_B16B16 (1UL << 45) #define HWCAP2_LRCPC3 (1UL << 46) +#define HWCAP2_LSE128 (1UL << 47) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index a83934291037..6b3ac96ef717 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2789,6 +2789,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), + HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 0ba7e6cd8fee..a257da7b56fe 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -129,6 +129,7 @@ static const char *const hwcap_str[] = { [KERNEL_HWCAP_HBC] = "hbc", [KERNEL_HWCAP_SVE_B16B16] = "sveb16b16", [KERNEL_HWCAP_LRCPC3] = "lrcpc3", + [KERNEL_HWCAP_LSE128] = "lse128", }; #ifdef CONFIG_COMPAT diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 4794556e67e9..96cbeeab4eec 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1239,6 +1239,7 @@ EndEnum UnsignedEnum 23:20 ATOMIC 0b0000 NI 0b0010 IMP + 0b0011 FEAT_LSE128 EndEnum UnsignedEnum 19:16 CRC32 0b0000 NI |