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authorLaurent Pinchart <laurent.pinchart@ideasonboard.com>2021-04-13 04:29:59 +0200
committerMauro Carvalho Chehab <mchehab+huawei@kernel.org>2021-05-23 19:21:32 +0200
commit996f6f517dc79f337faf29d9db54ceb9a3169787 (patch)
tree136329aa354946cf56f501d4279e100c32d58343
parentb329650e3f2d4369ec66e2fae2227beb7de37bca (diff)
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media: imx: imx7_mipi_csis: Set the CLKSETTLE register field
Set the CLKSETTLE field explicitly, with a value hardcoded to 0. This brings no functional change, but prepares for calculation of the CLKSETTLE value. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Rui Miguel Silva <rmfrfs@gmail.com> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
-rw-r--r--drivers/staging/media/imx/imx7-mipi-csis.c14
1 files changed, 10 insertions, 4 deletions
diff --git a/drivers/staging/media/imx/imx7-mipi-csis.c b/drivers/staging/media/imx/imx7-mipi-csis.c
index 1831ff4cc629..5dc001a415d4 100644
--- a/drivers/staging/media/imx/imx7-mipi-csis.c
+++ b/drivers/staging/media/imx/imx7-mipi-csis.c
@@ -310,6 +310,7 @@ struct csi_state {
u32 clk_frequency;
u32 hs_settle;
+ u32 clk_settle;
struct reset_control *mrst;
@@ -540,11 +541,15 @@ static int mipi_csis_calculate_params(struct csi_state *state)
/*
* The HSSETTLE counter value is document in a table, but can also
- * easily be calculated.
+ * easily be calculated. Hardcode the CLKSETTLE value to 0 for now
+ * (which is documented as corresponding to CSI-2 v0.87 to v1.00) until
+ * we figure out how to compute it correctly.
*/
state->hs_settle = (lane_rate - 5000000) / 45000000;
- dev_dbg(state->dev, "lane rate %u, Ths_settle %u\n",
- lane_rate, state->hs_settle);
+ state->clk_settle = 0;
+
+ dev_dbg(state->dev, "lane rate %u, Tclk_settle %u, Ths_settle %u\n",
+ lane_rate, state->clk_settle, state->hs_settle);
return 0;
}
@@ -563,7 +568,8 @@ static void mipi_csis_set_params(struct csi_state *state)
__mipi_csis_set_format(state);
mipi_csis_write(state, MIPI_CSIS_DPHY_CMN_CTRL,
- MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(state->hs_settle));
+ MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(state->hs_settle) |
+ MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(state->clk_settle));
val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET)
| (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET)