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author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2017-10-31 23:23:15 +0100 |
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committer | Kevin Hilman <khilman@baylibre.com> | 2017-12-06 17:03:46 -0800 |
commit | 9bef306b6ba250e20e49efb08a447d4bf95b7184 (patch) | |
tree | 140c203d826b98fb2080bcfcbee3fa2369ab97eb | |
parent | 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323 (diff) | |
download | linux-stable-9bef306b6ba250e20e49efb08a447d4bf95b7184.tar.gz linux-stable-9bef306b6ba250e20e49efb08a447d4bf95b7184.tar.bz2 linux-stable-9bef306b6ba250e20e49efb08a447d4bf95b7184.zip |
ARM: dts: meson8b: add more L2 cache settings
Amlogic's vendor kernel prints these PL310 L2 cache controller settings
during boot:
8 ways, 2048 sets, CACHE_ID 0x4100a0c9, Cache size: 524288 B
AUX_CTRL 0x7ec60001, PERFETCH_CTRL 0x75000007, POWER_CTRL 0x00000000
TAG_LATENCY 0x00000111, DATA_LATENCY 0x00000222
Add the "prefetch-data", "prefetch-instr" and "arm,shared-override"
properties to get the same L2 cache controller configuration as the
vendor kernel.
Four differences still remain:
- L310_AUX_CTRL_EARLY_BRESP is enabled by the vendor kernel, however
this is only supported on Cortex-A9 cores (Meson8b has Cortex-A5 cores
though)
- L310_AUX_CTRL_NS_INT_CTRL is currently not supported by the cache-l2x0
driver
- bit 23 is set by the vendor kernel, but this is defined in cache-l2x0.h
- L310_AUX_CTRL_FULL_LINE_ZERO is enabled by the vendor kernel which is
also only supported on Cortex-A9 cores
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
-rw-r--r-- | arch/arm/boot/dts/meson8b.dtsi | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index d75e0ceda8bb..65e7d026f797 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -223,6 +223,9 @@ arm,data-latency = <3 3 3>; arm,tag-latency = <2 2 2>; arm,filter-ranges = <0x100000 0xc0000000>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,shared-override; }; &pwm_ab { |