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author | Shawn Guo <shawn.guo@linaro.org> | 2017-07-27 16:23:36 +0800 |
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committer | Thierry Reding <thierry.reding@gmail.com> | 2017-08-21 07:34:18 +0200 |
commit | acfc3e348c4132d44c433b784f83fe3a26e1e328 (patch) | |
tree | 16c821d9ec681f1ad355760817e0239c66ee66be | |
parent | 8a88b2a2017d1e7e80db53080baff591fd454722 (diff) | |
download | linux-stable-acfc3e348c4132d44c433b784f83fe3a26e1e328.tar.gz linux-stable-acfc3e348c4132d44c433b784f83fe3a26e1e328.tar.bz2 linux-stable-acfc3e348c4132d44c433b784f83fe3a26e1e328.zip |
dt-bindings: pwm: Add bindings doc for ZTE ZX PWM controller
It adds bindings document for ZTE ZX PWM controller. The device has two
clocks: PCLK and WCLK. The PCLK is for register access, and WCLK is the
reference clock for calculating period and duty cycles. Also, the device
supports polarity configuration, so #pwm-cells should be 3.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
-rw-r--r-- | Documentation/devicetree/bindings/pwm/pwm-zx.txt | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pwm/pwm-zx.txt b/Documentation/devicetree/bindings/pwm/pwm-zx.txt new file mode 100644 index 000000000000..a6bcc75c9164 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-zx.txt @@ -0,0 +1,22 @@ +ZTE ZX PWM controller + +Required properties: + - compatible: Should be "zte,zx296718-pwm". + - reg: Physical base address and length of the controller's registers. + - clocks : The phandle and specifier referencing the controller's clocks. + - clock-names: "pclk" for PCLK, "wclk" for WCLK to the PWM controller. The + PCLK is for register access, while WCLK is the reference clock for + calculating period and duty cycles. + - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of + the cells format. + +Example: + + pwm: pwm@1439000 { + compatible = "zte,zx296718-pwm"; + reg = <0x1439000 0x1000>; + clocks = <&lsp1crm LSP1_PWM_PCLK>, + <&lsp1crm LSP1_PWM_WCLK>; + clock-names = "pclk", "wclk"; + #pwm-cells = <3>; + }; |