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| author | Chris Brandt <chris.brandt@renesas.com> | 2016-08-05 09:36:03 -0400 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2016-08-08 11:56:46 +0100 |
| commit | aeb8f8cb1537450e99f7d8f1a1d84d55b0fc6b26 (patch) | |
| tree | 064b5eb030780ba3eed459949fcceeeb490f32b5 | |
| parent | 29b4817d4018df78086157ea3a55c1d9424a7cfc (diff) | |
| download | linux-stable-aeb8f8cb1537450e99f7d8f1a1d84d55b0fc6b26.tar.gz linux-stable-aeb8f8cb1537450e99f7d8f1a1d84d55b0fc6b26.tar.bz2 linux-stable-aeb8f8cb1537450e99f7d8f1a1d84d55b0fc6b26.zip | |
spi: rspi: Increase accuracy of bit rate for RZ
When you leave the clock divider at 0, 130kHz is the lowest you can go.
Also, by adjusting the clock divider you can get more accurate resolutions
for clock speeds lower than 16MHz. This patch uses the clock divider as
part of the bit rate setup.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
| -rw-r--r-- | drivers/spi/spi-rspi.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c index 818843336932..a816f07e168e 100644 --- a/drivers/spi/spi-rspi.c +++ b/drivers/spi/spi-rspi.c @@ -295,14 +295,24 @@ static int rspi_set_config_register(struct rspi_data *rspi, int access_size) static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size) { int spbr; + int div = 0; + unsigned long clksrc; /* Sets output mode, MOSI signal, and (optionally) loopback */ rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); + clksrc = clk_get_rate(rspi->clk); + while (div < 3) { + if (rspi->max_speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */ + break; + div++; + clksrc /= 2; + } + /* Sets transfer bit rate */ - spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), - 2 * rspi->max_speed_hz) - 1; + spbr = DIV_ROUND_UP(clksrc, 2 * rspi->max_speed_hz) - 1; rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); + rspi->spcmd |= div << 2; /* Disable dummy transmission, set byte access */ rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR); |