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authorLeon Elazar <leon.elazar@amd.com>2017-01-17 16:16:04 -0500
committerAlex Deucher <alexander.deucher@amd.com>2017-09-26 17:11:07 -0400
commitb565ff86aaebee65141a4a441f782a05962d4c14 (patch)
tree32830b48e7c9601c1faae9b459371b4eafdaa398
parent009432e58159e640e942092ca68d78f589549d14 (diff)
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drm/amd/display: Add missing MI masks
This will fix the memory Input programing with MST tiled display. This Fix should fix connectivity problems with MST tiled Display Signed-off-by: Leon Elazar <leon.elazar@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
index f90d586656ef..ec053c241901 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
@@ -92,6 +92,8 @@ struct dce_mem_input_registers {
.field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
#define MI_GFX8_TILE_MASK_SH_LIST(mask_sh, blk)\
+ SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
+ SFB(blk, GRPH_CONTROL, GRPH_BANK_WIDTH, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\