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| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2021-12-28 07:54:02 +0300 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2022-02-10 18:33:30 -0600 |
| commit | ba9b57dcac4f33bd836e64bbb9591d9adeb369d2 (patch) | |
| tree | 5b9ca09c16fefc43411d5695bb376cf43d4ae193 | |
| parent | 6985fdc0c80c4fe576a196a12c8be11501f5c3f2 (diff) | |
| download | linux-stable-ba9b57dcac4f33bd836e64bbb9591d9adeb369d2.tar.gz linux-stable-ba9b57dcac4f33bd836e64bbb9591d9adeb369d2.tar.bz2 linux-stable-ba9b57dcac4f33bd836e64bbb9591d9adeb369d2.zip | |
clk: qcom: gpucc-sdm660: use parent_hws instead of parent_data
If all parents are specified as clk_hw, we can use parent_hws instead of
parent_data.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211228045415.20543-4-dmitry.baryshkov@linaro.org
| -rw-r--r-- | drivers/clk/qcom/gpucc-sdm660.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/clk/qcom/gpucc-sdm660.c b/drivers/clk/qcom/gpucc-sdm660.c index 8271696d21b4..d6b38a0b063d 100644 --- a/drivers/clk/qcom/gpucc-sdm660.c +++ b/drivers/clk/qcom/gpucc-sdm660.c @@ -65,8 +65,8 @@ static struct clk_alpha_pll gpu_pll0_pll_out_main = { .num_vco = ARRAY_SIZE(gpu_vco), .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_pll0_pll_out_main", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpucc_cxo_clk.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gpucc_cxo_clk.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_ops, @@ -80,8 +80,8 @@ static struct clk_alpha_pll gpu_pll1_pll_out_main = { .num_vco = ARRAY_SIZE(gpu_vco), .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_pll1_pll_out_main", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpucc_cxo_clk.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gpucc_cxo_clk.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_ops, @@ -134,8 +134,8 @@ static struct clk_branch gpucc_gfx3d_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpucc_gfx3d_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gfx3d_clk_src.rcg.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gfx3d_clk_src.rcg.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, |