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authorKarimAllah Ahmed <karahmed@amazon.de>2018-03-03 05:33:10 +0100
committerBjorn Helgaas <bhelgaas@google.com>2018-03-19 14:55:17 -0500
commitbf4447fd1cb6158b60bd60a79998e1d029d31e68 (patch)
treeffc1c818597a76f15c82f2a5d14f6fd6f07a8794
parentbe20f6b063f51cd77d071b803ee24f23200dc559 (diff)
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PCI/IOV: Skip BAR sizing for VFs
Per PCIe r4.0, sec 9.3.4.1.11, the BAR registers in VF config space are all RO Zero, so skip sizing them. This is an optimization when enabling SR-IOV on a device with many VFs. Suggested-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: KarimAllah Ahmed <karahmed@amazon.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-rw-r--r--drivers/pci/probe.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index a1cddca37793..9f80b904bf76 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -329,6 +329,10 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
if (dev->non_compliant_bars)
return;
+ /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
+ if (dev->is_virtfn)
+ return;
+
for (pos = 0; pos < howmany; pos++) {
struct resource *res = &dev->resource[pos];
reg = PCI_BASE_ADDRESS_0 + (pos << 2);