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| author | Stefan Agner <stefan@agner.ch> | 2018-04-18 14:49:08 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-06-21 04:03:00 +0900 |
| commit | c5746752bdbe4e7c6512d581dce5cc4ebc45ae75 (patch) | |
| tree | 7520c6f06f102186f308fb972d16b2bc8a80a955 | |
| parent | 0c5dfa51caf77461da90b3af1f1ec28490255bc0 (diff) | |
| download | linux-stable-c5746752bdbe4e7c6512d581dce5cc4ebc45ae75.tar.gz linux-stable-c5746752bdbe4e7c6512d581dce5cc4ebc45ae75.tar.bz2 linux-stable-c5746752bdbe4e7c6512d581dce5cc4ebc45ae75.zip | |
clk: imx6ull: use OSC clock during AXI rate change
[ Upstream commit 2e5be528ab0182ad4b42b9feea3b80f85f37179b ]
On i.MX6 ULL using PLL3 seems to cause a freeze when setting
the parent to IMX6UL_CLK_PLL3_USB_OTG. This only seems to appear
since commit 6f9575e55632 ("clk: imx: Add CLK_IS_CRITICAL flag
for busy divider and busy mux"), probably because the clock is
now forced to be on.
Fixes: 6f9575e55632("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux")
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | drivers/clk/imx/clk-imx6ul.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c index 5e8c18afce9a..41c08fc892b9 100644 --- a/drivers/clk/imx/clk-imx6ul.c +++ b/drivers/clk/imx/clk-imx6ul.c @@ -461,7 +461,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clk_set_rate(clks[IMX6UL_CLK_AHB], 99000000); /* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */ - clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]); + clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_OSC]); clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_CLK2]); clk_set_parent(clks[IMX6UL_CLK_PERIPH_PRE], clks[IMX6UL_CLK_PLL2_BUS]); clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_PRE]); |