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| author | Prabhjot Khurana <prabhjot.khurana@intel.com> | 2021-10-20 11:35:37 +0100 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2021-10-29 21:04:03 +0800 |
| commit | cadddc89a0445bbd5133f4f4523e07a9ce4c6e52 (patch) | |
| tree | f44ada66fda60ad9eb551c8ea6a91aa31a2aeece | |
| parent | eaffe377e168d25c52091cf31f5a7a6511897857 (diff) | |
| download | linux-stable-cadddc89a0445bbd5133f4f4523e07a9ce4c6e52.tar.gz linux-stable-cadddc89a0445bbd5133f4f4523e07a9ce4c6e52.tar.bz2 linux-stable-cadddc89a0445bbd5133f4f4523e07a9ce4c6e52.zip | |
dt-bindings: crypto: Add Keem Bay ECC bindings
Add Keem Bay Offload and Crypto Subsystem (OCS) Elliptic Curve
Cryptography (ECC) device tree bindings.
Signed-off-by: Prabhjot Khurana <prabhjot.khurana@intel.com>
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| -rw-r--r-- | Documentation/devicetree/bindings/crypto/intel,keembay-ocs-ecc.yaml | 47 | ||||
| -rw-r--r-- | MAINTAINERS | 7 |
2 files changed, 54 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/crypto/intel,keembay-ocs-ecc.yaml b/Documentation/devicetree/bindings/crypto/intel,keembay-ocs-ecc.yaml new file mode 100644 index 000000000000..a3c16451b1ad --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/intel,keembay-ocs-ecc.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-ecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay OCS ECC Device Tree Bindings + +maintainers: + - Daniele Alessandrelli <daniele.alessandrelli@intel.com> + - Prabhjot Khurana <prabhjot.khurana@intel.com> + +description: + The Intel Keem Bay Offload and Crypto Subsystem (OCS) Elliptic Curve + Cryptography (ECC) device provides hardware acceleration for elliptic curve + cryptography using the NIST P-256 and NIST P-384 elliptic curves. + +properties: + compatible: + const: intel,keembay-ocs-ecc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + crypto@30001000 { + compatible = "intel,keembay-ocs-ecc"; + reg = <0x30001000 0x1000>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk 95>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index eeb4c70b3d5b..c588801a7b12 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9512,6 +9512,13 @@ F: drivers/crypto/keembay/keembay-ocs-aes-core.c F: drivers/crypto/keembay/ocs-aes.c F: drivers/crypto/keembay/ocs-aes.h +INTEL KEEM BAY OCS ECC CRYPTO DRIVER +M: Daniele Alessandrelli <daniele.alessandrelli@intel.com> +M: Prabhjot Khurana <prabhjot.khurana@intel.com> +M: Mark Gross <mgross@linux.intel.com> +S: Maintained +F: Documentation/devicetree/bindings/crypto/intel,keembay-ocs-ecc.yaml + INTEL KEEM BAY OCS HCU CRYPTO DRIVER M: Daniele Alessandrelli <daniele.alessandrelli@intel.com> M: Declan Murphy <declan.murphy@intel.com> |