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author | Sinan Kaya <okaya@codeaurora.org> | 2018-04-03 08:55:03 -0400 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-06-21 04:02:40 +0900 |
commit | d96da2acac5dcf3d8187794b5ef86481ddcf2791 (patch) | |
tree | ffcfe03433687f1d1afc5671300e6457e5f8712c | |
parent | df5524e5483b6a29c011721131a510fae3ce0f45 (diff) | |
download | linux-stable-d96da2acac5dcf3d8187794b5ef86481ddcf2791.tar.gz linux-stable-d96da2acac5dcf3d8187794b5ef86481ddcf2791.tar.bz2 linux-stable-d96da2acac5dcf3d8187794b5ef86481ddcf2791.zip |
MIPS: io: Prevent compiler reordering writeX()
[ Upstream commit f6b7aeee8f167409195fbf1364d02988fecad1d0 ]
writeX() has strong ordering semantics with respect to memory updates.
In the absence of a write barrier or a compiler barrier, the compiler
can reorder register and memory update instructions. This breaks the
writeX() API.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/18997/
[jhogan@kernel.org: Tidy commit message]
Signed-off-by: James Hogan <jhogan@kernel.org>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r-- | arch/mips/include/asm/io.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 0cbf3af37eca..fd00ddafb425 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -307,7 +307,7 @@ static inline void iounmap(const volatile void __iomem *addr) #if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_LOONGSON3_ENHANCEMENT) #define war_io_reorder_wmb() wmb() #else -#define war_io_reorder_wmb() do { } while (0) +#define war_io_reorder_wmb() barrier() #endif #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \ |