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| author | Mayuresh Chitale <mchitale@ventanamicro.com> | 2022-01-31 16:33:07 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2022-02-02 18:57:10 +0530 |
| commit | de1d7b6a51dab546160d252e47baa54adf104d4a (patch) | |
| tree | c117b1965faee627f35a6f8d73d7fffbc2c85e73 | |
| parent | 6455317e4d0d8395e8e4a2fd1ec8d6502267dd02 (diff) | |
| download | linux-stable-de1d7b6a51dab546160d252e47baa54adf104d4a.tar.gz linux-stable-de1d7b6a51dab546160d252e47baa54adf104d4a.tar.bz2 linux-stable-de1d7b6a51dab546160d252e47baa54adf104d4a.zip | |
RISC-V: KVM: make CY, TM, and IR counters accessible in VU mode
Those applications that run in VU mode and access the time CSR cause
a virtual instruction trap as Guest kernel currently does not
initialize the scounteren CSR.
To fix this, we should make CY, TM, and IR counters accessibile
by default in VU mode (similar to OpenSBI).
Fixes: a33c72faf2d73 ("RISC-V: KVM: Implement VCPU create, init and
destroy functions")
Cc: stable@vger.kernel.org
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
| -rw-r--r-- | arch/riscv/kvm/vcpu.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index f64f62057378..624166004e36 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -90,6 +90,7 @@ int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) { struct kvm_cpu_context *cntx; + struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr; /* Mark this VCPU never ran */ vcpu->arch.ran_atleast_once = false; @@ -106,6 +107,9 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) cntx->hstatus |= HSTATUS_SPVP; cntx->hstatus |= HSTATUS_SPV; + /* By default, make CY, TM, and IR counters accessible in VU mode */ + reset_csr->scounteren = 0x7; + /* Setup VCPU timer */ kvm_riscv_vcpu_timer_init(vcpu); |