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| author | Changbin Du <changbin.du@intel.com> | 2017-04-06 10:55:02 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2017-04-12 13:57:42 +0800 |
| commit | e1236bc06c534a97f73e09aed5e1094108553e9f (patch) | |
| tree | 16faf6807220b91820833a47fcc9818a93a46801 | |
| parent | 0b063bd3ea9c13df78c82aa742e581c39f9d6156 (diff) | |
| download | linux-stable-e1236bc06c534a97f73e09aed5e1094108553e9f.tar.gz linux-stable-e1236bc06c534a97f73e09aed5e1094108553e9f.tar.bz2 linux-stable-e1236bc06c534a97f73e09aed5e1094108553e9f.zip | |
drm/i915/gvt: Align render mmio list to cacheline
Make the global mmio list be cacheline aligned to improve performance.
Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/render.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c index e24e57afc45e..679411fe653f 100644 --- a/drivers/gpu/drm/i915/gvt/render.c +++ b/drivers/gpu/drm/i915/gvt/render.c @@ -44,7 +44,7 @@ struct render_mmio { u32 value; }; -static struct render_mmio gen8_render_mmio_list[] = { +static struct render_mmio gen8_render_mmio_list[] __cacheline_aligned = { {RCS, _MMIO(0x229c), 0xffff, false}, {RCS, _MMIO(0x2248), 0x0, false}, {RCS, _MMIO(0x2098), 0x0, false}, @@ -75,7 +75,7 @@ static struct render_mmio gen8_render_mmio_list[] = { {BCS, _MMIO(0x22028), 0x0, false}, }; -static struct render_mmio gen9_render_mmio_list[] = { +static struct render_mmio gen9_render_mmio_list[] __cacheline_aligned = { {RCS, _MMIO(0x229c), 0xffff, false}, {RCS, _MMIO(0x2248), 0x0, false}, {RCS, _MMIO(0x2098), 0x0, false}, |