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author | Stephen Boyd <sboyd@kernel.org> | 2019-03-08 10:29:30 -0800 |
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committer | Stephen Boyd <sboyd@kernel.org> | 2019-03-08 10:29:30 -0800 |
commit | efb1e0b07139974b506c90f4e0621d5866ee48b7 (patch) | |
tree | 2f320c3eefa309610aa1f6223f51ec682196f56c | |
parent | 75f486c015b51d00412f0671e3dfbb45b42f27ce (diff) | |
parent | 635bd69bbe92acfeddcc6f3d7e7eb1a9049f361b (diff) | |
parent | d3174bc836d5aadc871f74ed496694c5ea27b104 (diff) | |
parent | 4b5a59a265f05a41df6bb3449d8c6db50577dca5 (diff) | |
parent | b35656de2a13298512a558506fa8d97a9eda5494 (diff) | |
parent | 64f4466c887e2f16cb01467c8064ff1106c980a3 (diff) | |
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Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', 'clk-mtk-crit' and 'clk-mtk' into clk-next
* clk-ingenic:
clk: ingenic: Remove set but not used variable 'enable'
clk: ingenic: Fix doc of ingenic_cgu_div_info
clk: ingenic: Fix round_rate misbehaving with non-integer dividers
clk: ingenic: jz4740: Fix gating of UDC clock
* clk-mtk-mux:
clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel
clk: mediatek: add MUX_GATE_FLAGS_2
* clk-qcom-sdm845-pcie:
clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks
* clk-mtk-crit:
clk: mediatek: Mark bus and DRAM related clocks as critical
clk: mediatek: Add flags to mtk_gate
clk: mediatek: Add MUX_FLAGS macro
* clk-mtk:
clk: mediatek: correct cpu clock name for MT8173 SoC