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| author | John Watts <contact@jookia.org> | 2023-08-08 05:19:52 +1000 |
|---|---|---|
| committer | Chen-Yu Tsai <wens@csie.org> | 2023-08-13 14:12:35 +0800 |
| commit | f05af44f691351bfd954f39ec376666dc5e1b869 (patch) | |
| tree | 55ab37125dac7e3259500584eb79fdc40cc43217 | |
| parent | 0801a3a9f35854c91f1f3ab8e879c3d14912d214 (diff) | |
| download | linux-stable-f05af44f691351bfd954f39ec376666dc5e1b869.tar.gz linux-stable-f05af44f691351bfd954f39ec376666dc5e1b869.tar.bz2 linux-stable-f05af44f691351bfd954f39ec376666dc5e1b869.zip | |
riscv: dts: allwinner: d1: Add CAN controller nodes
The Allwinner D1, T113 provide two CAN controllers that are variants
of the R40 controller.
I have tested support for these controllers on two boards:
- A Lichee Panel RV 86 Panel running a D1 chip
- A Mango Pi MQ Dual running a T113-s3 chip
Both of these fully support both CAN controllers.
Signed-off-by: John Watts <contact@jookia.org>
Link: https://lore.kernel.org/r/20230807191952.2019208-1-contact@jookia.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
| -rw-r--r-- | arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index d59b4acf183a..822f022eec2d 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -53,6 +53,18 @@ #interrupt-cells = <3>; /omit-if-no-ref/ + can0_pins: can0-pins { + pins = "PB2", "PB3"; + function = "can0"; + }; + + /omit-if-no-ref/ + can1_pins: can1-pins { + pins = "PB4", "PB5"; + function = "can1"; + }; + + /omit-if-no-ref/ clk_pg11_pin: clk-pg11-pin { pins = "PG11"; function = "clk"; @@ -356,6 +368,28 @@ #size-cells = <0>; }; + can0: can@2504000 { + compatible = "allwinner,sun20i-d1-can"; + reg = <0x02504000 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(21) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CAN0>; + resets = <&ccu RST_BUS_CAN0>; + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins>; + status = "disabled"; + }; + + can1: can@2504400 { + compatible = "allwinner,sun20i-d1-can"; + reg = <0x02504400 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CAN1>; + resets = <&ccu RST_BUS_CAN1>; + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins>; + status = "disabled"; + }; + syscon: syscon@3000000 { compatible = "allwinner,sun20i-d1-system-control"; reg = <0x3000000 0x1000>; |