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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-06-06 22:14:47 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-09-27 18:35:29 +0300 |
| commit | fa1b97f85d3bee4e9a6d6626817ab5f83a7b1b85 (patch) | |
| tree | cbd6c6d33dabbd929e7d0c19f46d5b33f59a8bc0 | |
| parent | f067976e4939133e656ce4532995ba96bfe68366 (diff) | |
| download | linux-stable-fa1b97f85d3bee4e9a6d6626817ab5f83a7b1b85.tar.gz linux-stable-fa1b97f85d3bee4e9a6d6626817ab5f83a7b1b85.tar.bz2 linux-stable-fa1b97f85d3bee4e9a6d6626817ab5f83a7b1b85.zip | |
drm/i915/dsb: Use non-locked register access
Avoid the locking overhead for DSB registers. We don't need the locks
and intel_dsb_commit() in particular needs to be called from the
vblank evade critical section and thus needs to be fast.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230606191504.18099-3-ville.syrjala@linux.intel.com
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dsb.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 9a507b9ad82c..52569dc8849e 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -112,7 +112,7 @@ static void intel_dsb_dump(struct intel_dsb *dsb) static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe, enum dsb_id id) { - return intel_de_read(i915, DSB_CTRL(pipe, id)) & DSB_STATUS_BUSY; + return intel_de_read_fw(i915, DSB_CTRL(pipe, id)) & DSB_STATUS_BUSY; } static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw) @@ -273,13 +273,13 @@ void intel_dsb_commit(struct intel_dsb *dsb, bool wait_for_vblank) return; } - intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id), - (wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0) | - DSB_ENABLE); - intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id), - i915_ggtt_offset(dsb->vma)); - intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id), - i915_ggtt_offset(dsb->vma) + tail); + intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id), + (wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0) | + DSB_ENABLE); + intel_de_write_fw(dev_priv, DSB_HEAD(pipe, dsb->id), + i915_ggtt_offset(dsb->vma)); + intel_de_write_fw(dev_priv, DSB_TAIL(pipe, dsb->id), + i915_ggtt_offset(dsb->vma) + tail); } void intel_dsb_wait(struct intel_dsb *dsb) @@ -307,7 +307,7 @@ void intel_dsb_wait(struct intel_dsb *dsb) /* Attempt to reset it */ dsb->free_pos = 0; dsb->ins_start_offset = 0; - intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id), 0); + intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id), 0); } /** |