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| author | Tony Luck <tony.luck@intel.com> | 2021-03-19 10:39:19 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-02-05 12:37:55 +0100 |
| commit | fbdbf6743f777729aadd00c4444234770f8dd042 (patch) | |
| tree | 0b10faaf3e5fbae6fc055ad8809ed9ab6bc9e413 | |
| parent | d4e4e61d4a5b87bfc9953c306a11d35d869417fd (diff) | |
| download | linux-stable-fbdbf6743f777729aadd00c4444234770f8dd042.tar.gz linux-stable-fbdbf6743f777729aadd00c4444234770f8dd042.tar.bz2 linux-stable-fbdbf6743f777729aadd00c4444234770f8dd042.zip | |
x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN
commit a331f5fdd36dba1ffb0239a4dfaaf1df91ff1aab upstream.
New CPU model, same MSRs to control and read the inventory number.
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20210319173919.291428-1-tony.luck@intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | arch/x86/kernel/cpu/mce/intel.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index 2577d7875781..7cf08c1f082e 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -486,6 +486,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c) case INTEL_FAM6_BROADWELL_X: case INTEL_FAM6_SKYLAKE_X: case INTEL_FAM6_ICELAKE_X: + case INTEL_FAM6_SAPPHIRERAPIDS_X: case INTEL_FAM6_XEON_PHI_KNL: case INTEL_FAM6_XEON_PHI_KNM: |