diff options
author | Qingqing Zhuo <Qingqing.Zhuo@amd.com> | 2023-08-03 01:40:34 -0400 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2023-08-30 15:51:14 -0400 |
commit | ffb8c23718e4106a56735b9ff5a21f0d876ca923 (patch) | |
tree | 139e11d3e490ac64f17a3d52cfa6f945b768df58 | |
parent | b9c96af677cbed62c07272594312cc8198293a24 (diff) | |
download | linux-stable-ffb8c23718e4106a56735b9ff5a21f0d876ca923.tar.gz linux-stable-ffb8c23718e4106a56735b9ff5a21f0d876ca923.tar.bz2 linux-stable-ffb8c23718e4106a56735b9ff5a21f0d876ca923.zip |
drm/amd/display: Add DCN35 OPP
[Why & How]
Add OPP handling for DCN35.
Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn35/dcn35_opp.c | 51 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn35/dcn35_opp.h | 65 |
2 files changed, 116 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_opp.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_opp.c new file mode 100644 index 000000000000..d79e8c6365c1 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_opp.c @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "dcn35_opp.h" +#include "reg_helper.h" + +#define REG(reg) ((const struct dcn35_opp_registers *)(oppn20->regs))->reg + +#undef FN +#define FN(reg_name, field_name) \ + ((const struct dcn35_opp_shift *)(oppn20->opp_shift))->field_name, \ + ((const struct dcn35_opp_mask *)(oppn20->opp_mask))->field_name + +#define CTX oppn20->base.ctx + +void dcn35_opp_construct(struct dcn20_opp *oppn20, struct dc_context *ctx, + uint32_t inst, const struct dcn35_opp_registers *regs, + const struct dcn35_opp_shift *opp_shift, + const struct dcn35_opp_mask *opp_mask) +{ + dcn20_opp_construct(oppn20, ctx, inst, + (const struct dcn20_opp_registers *)regs, + (const struct dcn20_opp_shift *)opp_shift, + (const struct dcn20_opp_mask *)opp_mask); +} + +void dcn35_opp_set_fgcg(struct dcn20_opp *oppn20, bool enable) +{ + REG_UPDATE(OPP_TOP_CLK_CONTROL, OPP_FGCG_REP_DIS, !enable); +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_opp.h b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_opp.h new file mode 100644 index 000000000000..9dd21b104287 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_opp.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __DCN35_OPP_H +#define __DCN35_OPP_H + +#include "dcn20/dcn20_opp.h" + +#define OPP_REG_VARIABLE_LIST_DCN3_5 \ + OPP_REG_VARIABLE_LIST_DCN2_0; \ + uint32_t OPP_TOP_CLK_CONTROL + +#define OPP_MASK_SH_LIST_DCN35(mask_sh) \ + OPP_MASK_SH_LIST_DCN20(mask_sh), \ + OPP_SF(OPP_TOP_CLK_CONTROL, OPP_FGCG_REP_DIS, mask_sh) + +#define OPP_DCN35_REG_FIELD_LIST(type) \ + struct { \ + OPP_DCN20_REG_FIELD_LIST(type); \ + type OPP_FGCG_REP_DIS; \ + } + +struct dcn35_opp_registers { + OPP_REG_VARIABLE_LIST_DCN3_5; +}; + +struct dcn35_opp_shift { + OPP_DCN35_REG_FIELD_LIST(uint8_t); +}; + +struct dcn35_opp_mask { + OPP_DCN35_REG_FIELD_LIST(uint32_t); +}; + +void dcn35_opp_construct(struct dcn20_opp *oppn20, + struct dc_context *ctx, + uint32_t inst, + const struct dcn35_opp_registers *regs, + const struct dcn35_opp_shift *opp_shift, + const struct dcn35_opp_mask *opp_mask); + +void dcn35_opp_set_fgcg(struct dcn20_opp *oppn20, bool enable); + +#endif |