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| author | Florian Fainelli <f.fainelli@gmail.com> | 2018-08-31 12:20:39 -0700 |
|---|---|---|
| committer | Florian Fainelli <f.fainelli@gmail.com> | 2018-09-13 11:09:33 -0700 |
| commit | ccf8b4e4eb6b358a1ee445d9c9de507356360451 (patch) | |
| tree | 8f05a67d0b1ba2489d90b97da793125d1474cf30 /COPYING | |
| parent | 56512ffd2923fbe9665e84026074da96273dcb61 (diff) | |
| download | linux-stable-ccf8b4e4eb6b358a1ee445d9c9de507356360451.tar.gz linux-stable-ccf8b4e4eb6b358a1ee445d9c9de507356360451.tar.bz2 linux-stable-ccf8b4e4eb6b358a1ee445d9c9de507356360451.zip | |
ARM: dts: NSP: Wire up switch interrupts
The Switch Register Access Block (SRAB) has one interrupt for link state
change on each ports (0-5, 7-8) a PHY interrupt, timestamping interrupt
and sleep timer interrupts for each management ports (5,7,8). Wire those
up so we can utilize them to speed up link resolution.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'COPYING')
0 files changed, 0 insertions, 0 deletions