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authorIngo Molnar <mingo@elte.hu>2009-11-04 11:54:15 +0100
committerIngo Molnar <mingo@elte.hu>2009-11-04 11:59:45 +0100
commita2e71271535fde493c32803b1f34789f97efcb5e (patch)
tree90d7139bea2f49e947f27af92614fa6eca50b64d /Documentation/ABI/testing/sysfs-devices-cache_disable
parent6d7aa9d721c8c640066142fd9534afcdf68d7f9d (diff)
parentb419148e567728f6af0c3b01965c1cc141e3e13a (diff)
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Merge commit 'v2.6.32-rc6' into perf/core
Conflicts: tools/perf/Makefile Merge reason: Resolve the conflict, merge to upstream and merge in perf fixes so we can add a dependent patch. Signed-off-by: Ingo Molnar <mingo@elte.hu>
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-What: /sys/devices/system/cpu/cpu*/cache/index*/cache_disable_X
-Date: August 2008
-KernelVersion: 2.6.27
-Contact: mark.langsdorf@amd.com
-Description: These files exist in every cpu's cache index directories.
- There are currently 2 cache_disable_# files in each
- directory. Reading from these files on a supported
- processor will return that cache disable index value
- for that processor and node. Writing to one of these
- files will cause the specificed cache index to be disabled.
-
- Currently, only AMD Family 10h Processors support cache index
- disable, and only for their L3 caches. See the BIOS and
- Kernel Developer's Guide at
- http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116-Public-GH-BKDG_3.20_2-4-09.pdf
- for formatting information and other details on the
- cache index disable.
-Users: joachim.deguara@amd.com