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author | Arnaldo Carvalho de Melo <acme@redhat.com> | 2023-08-04 10:06:38 -0300 |
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committer | Arnaldo Carvalho de Melo <acme@redhat.com> | 2023-08-04 10:06:38 -0300 |
commit | bf1842996aaa726bf3d108b41f366b88680acbe6 (patch) | |
tree | e00bac5f0191e8e6dc8be26f2efda8c073051e9e /Documentation/admin-guide | |
parent | f6b8436bede3e80226e8b2100279c4450c73806a (diff) | |
parent | c1a515d3c0270628df8ae5f5118ba859b85464a2 (diff) | |
download | linux-stable-bf1842996aaa726bf3d108b41f366b88680acbe6.tar.gz linux-stable-bf1842996aaa726bf3d108b41f366b88680acbe6.tar.bz2 linux-stable-bf1842996aaa726bf3d108b41f366b88680acbe6.zip |
Merge remote-tracking branch 'torvalds/master' into perf-tools-next
To pick up the fixes that were just merged from perf-tools/perf-tools
for v6.5.
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'Documentation/admin-guide')
-rw-r--r-- | Documentation/admin-guide/devices.txt | 2 | ||||
-rw-r--r-- | Documentation/admin-guide/hw-vuln/spectre.rst | 11 |
2 files changed, 8 insertions, 5 deletions
diff --git a/Documentation/admin-guide/devices.txt b/Documentation/admin-guide/devices.txt index 06c525e01ea5..b1b57f638b94 100644 --- a/Documentation/admin-guide/devices.txt +++ b/Documentation/admin-guide/devices.txt @@ -2691,7 +2691,7 @@ 45 = /dev/ttyMM1 Marvell MPSC - port 1 (obsolete unused) 46 = /dev/ttyCPM0 PPC CPM (SCC or SMC) - port 0 ... - 47 = /dev/ttyCPM5 PPC CPM (SCC or SMC) - port 5 + 49 = /dev/ttyCPM5 PPC CPM (SCC or SMC) - port 3 50 = /dev/ttyIOC0 Altix serial card ... 81 = /dev/ttyIOC31 Altix serial card diff --git a/Documentation/admin-guide/hw-vuln/spectre.rst b/Documentation/admin-guide/hw-vuln/spectre.rst index 4d186f599d90..32a8893e5617 100644 --- a/Documentation/admin-guide/hw-vuln/spectre.rst +++ b/Documentation/admin-guide/hw-vuln/spectre.rst @@ -484,11 +484,14 @@ Spectre variant 2 Systems which support enhanced IBRS (eIBRS) enable IBRS protection once at boot, by setting the IBRS bit, and they're automatically protected against - Spectre v2 variant attacks, including cross-thread branch target injections - on SMT systems (STIBP). In other words, eIBRS enables STIBP too. + Spectre v2 variant attacks. - Legacy IBRS systems clear the IBRS bit on exit to userspace and - therefore explicitly enable STIBP for that + On Intel's enhanced IBRS systems, this includes cross-thread branch target + injections on SMT systems (STIBP). In other words, Intel eIBRS enables + STIBP, too. + + AMD Automatic IBRS does not protect userspace, and Legacy IBRS systems clear + the IBRS bit on exit to userspace, therefore both explicitly enable STIBP. The retpoline mitigation is turned on by default on vulnerable CPUs. It can be forced on or off by the administrator |