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| author | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-03-23 17:38:26 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-04-22 00:29:23 +0200 |
| commit | fa4d0ca104bfdcda7b7e2bac855b358f302fd310 (patch) | |
| tree | 14c68c6b45413a4281a7d53af3b84564400a4bf1 /Documentation/devicetree/bindings/clock/sunxi.txt | |
| parent | 7f2ea3847d47d49929d41573a3b26c80ddebbef5 (diff) | |
| download | linux-stable-fa4d0ca104bfdcda7b7e2bac855b358f302fd310.tar.gz linux-stable-fa4d0ca104bfdcda7b7e2bac855b358f302fd310.tar.bz2 linux-stable-fa4d0ca104bfdcda7b7e2bac855b358f302fd310.zip | |
clk: sunxi: Add PLL3 clock
The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
PLL7, clocked from a 3MHz oscillator, that drives the display related
clocks (GPU, display engine, TCON, etc.)
Add a driver for it.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/sunxi.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/sunxi.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 1bf588e11d46..005a24c6bd74 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -10,6 +10,7 @@ Required properties: "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23 + "allwinner,sun4i-a10-pll3-clk" - for the video PLL clock on A10 "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80 "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock |