summaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree/bindings/clock
diff options
context:
space:
mode:
authorStephen Boyd <sboyd@kernel.org>2019-03-08 10:27:52 -0800
committerStephen Boyd <sboyd@kernel.org>2019-03-08 10:27:52 -0800
commit461ea6ab2c49177bcc7b5a8aa54d614099668815 (patch)
treeb4adb29883a575a138ab6e8f069462764e9a9ac5 /Documentation/devicetree/bindings/clock
parente7faa095cbd761ec9e0c0dd83a7425b19ddce510 (diff)
parent04053f4d23a41b9383dcea4da302fd43f673afb3 (diff)
parentc0189feeade0f02a6cdac3b27b5e9c52f9930fc2 (diff)
parent585fc46bd47a143ee7433768e298a7f94008e5f5 (diff)
parent9d575719ca9b8e177391addb2855be3911dc0d93 (diff)
parented6b4795ece45e43856f6a42571d477695173742 (diff)
downloadlinux-stable-461ea6ab2c49177bcc7b5a8aa54d614099668815.tar.gz
linux-stable-461ea6ab2c49177bcc7b5a8aa54d614099668815.tar.bz2
linux-stable-461ea6ab2c49177bcc7b5a8aa54d614099668815.zip
Merge branches 'clk-qcom-rpmh', 'clk-gpio-sleep', 'clk-stm32mp1', 'clk-qcom-qcs404' and 'clk-actions-s500' into clk-next
- IPA clk support on Qualcomm RPMh clk controllers - Support sleeping gpios in clk-gpio type - Minor fixes for STM32MP1 clk driver (parents, critical flag, etc.) - Actions Semi S500 SoC clk support * clk-qcom-rpmh: clk: qcom: clk-rpmh: Add IPA clock support * clk-gpio-sleep: clk: clk-gpio: add support for sleeping GPIOs in gpio-gate-clk * clk-stm32mp1: dt-bindings: clock: remove unused definition for stm32mp1 clk: stm32mp1: fix bit width of hse_rtc divider clk: stm32mp1: remove unnecessary CLK_DIVIDER_ALLOW_ZERO flag clk: stm32mp1: fix HSI divider flag clk: stm32mp1: fix mcu divider table clk: stm32mp1: set ck_csi as critical clock clk: stm32mp1: add CLK_SET_RATE_NO_REPARENT to Kernel clocks clk: stm32mp1: parent clocks update * clk-qcom-qcs404: clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs clk: qcom: remove empty lines in clk-rcg.h * clk-actions-s500: clk: actions: Add clock driver for S500 SoC dt-bindings: clock: Add DT bindings for Actions Semi S500 CMU clk: actions: Add configurable PLL delay