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author | Krishna Manikandan <mkrishn@codeaurora.org> | 2021-05-24 17:14:12 +0530 |
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committer | Rob Clark <robdclark@chromium.org> | 2021-05-24 15:54:45 -0700 |
commit | 8fc939e72ff80116c090aaf03952253a124d2a8e (patch) | |
tree | 30a4dbffcf4905decec4fe9836b6466d46516098 /Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml | |
parent | 4dbe55c9774179da9630498e647c718d1c910bca (diff) | |
download | linux-stable-8fc939e72ff80116c090aaf03952253a124d2a8e.tar.gz linux-stable-8fc939e72ff80116c090aaf03952253a124d2a8e.tar.bz2 linux-stable-8fc939e72ff80116c090aaf03952253a124d2a8e.zip |
dt-bindings: msm: dsi: add yaml schemas for DSI PHY bindings
Add YAML schema for the device tree bindings for DSI PHY.
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1621856653-10649-3-git-send-email-mkrishn@codeaurora.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml new file mode 100644 index 000000000000..4a26bef19360 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DSI 10nm PHY + +maintainers: + - Krishna Manikandan <mkrishn@codeaurora.org> + +allOf: + - $ref: dsi-phy-common.yaml# + +properties: + compatible: + oneOf: + - const: qcom,dsi-phy-10nm + - const: qcom,dsi-phy-10nm-8998 + + reg: + items: + - description: dsi phy register set + - description: dsi phy lane register set + - description: dsi pll register set + + reg-names: + items: + - const: dsi_phy + - const: dsi_phy_lane + - const: dsi_pll + + vdds-supply: + description: | + Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and + connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target + +required: + - compatible + - reg + - reg-names + - vdds-supply + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sdm845.h> + #include <dt-bindings/clock/qcom,rpmh.h> + + dsi-phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94a00 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + vdds-supply = <&vdda_mipi_dsi0_pll>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + }; +... |