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| author | Moudy Ho <moudy.ho@mediatek.com> | 2023-10-31 16:33:56 +0800 |
|---|---|---|
| committer | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2023-12-11 11:13:04 +0100 |
| commit | 739058a9c5c31181a3f5599c30690be82d252428 (patch) | |
| tree | 69a58412d72f1cbf5210d2e14b74996e99fb43c6 /Documentation/devicetree/bindings/display | |
| parent | fe49f432abf267a167cb4318093e97c92f21dae6 (diff) | |
| download | linux-stable-739058a9c5c31181a3f5599c30690be82d252428.tar.gz linux-stable-739058a9c5c31181a3f5599c30690be82d252428.tar.bz2 linux-stable-739058a9c5c31181a3f5599c30690be82d252428.zip | |
dt-bindings: display: mediatek: split: add compatible for MT8195
Add compatible string and GCE property for MT8195 SPLIT, of
which is operated by MDP3.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Diffstat (limited to 'Documentation/devicetree/bindings/display')
| -rw-r--r-- | Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml index a8a5c9608598..e4affc854f3d 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml @@ -23,6 +23,7 @@ properties: oneOf: - enum: - mediatek,mt8173-disp-split + - mediatek,mt8195-mdp3-split - items: - const: mediatek,mt6795-disp-split - const: mediatek,mt8173-disp-split @@ -38,6 +39,21 @@ properties: the power controller specified by phandle. See Documentation/devicetree/bindings/power/power-domain.yaml for details. + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4 arguments, + such as gce node, subsys id, offset and register size. The subsys id that is + mapping to the register of display function blocks is defined in the gce header + include/dt-bindings/gce/<chip>-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + maxItems: 1 + clocks: items: - description: SPLIT Clock @@ -48,6 +64,17 @@ required: - power-domains - clocks +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt8195-mdp3-split + + then: + required: + - mediatek,gce-client-reg + additionalProperties: false examples: |