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| author | Marek Vasut <marex@denx.de> | 2022-09-27 00:20:03 +0200 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2022-10-17 17:49:17 -0400 |
| commit | 97c742d92f3b11353842c1fcb67e9811cc17bde3 (patch) | |
| tree | 446b65db3f30fc18e3971ef92c0c1a871a69731d /Documentation/devicetree/bindings/memory-controllers | |
| parent | 9abf2313adc1ca1b6180c508c25f22f9395cc780 (diff) | |
| download | linux-stable-97c742d92f3b11353842c1fcb67e9811cc17bde3.tar.gz linux-stable-97c742d92f3b11353842c1fcb67e9811cc17bde3.tar.bz2 linux-stable-97c742d92f3b11353842c1fcb67e9811cc17bde3.zip | |
dt-bindings: memory-controller: st,stm32: Fix st,fmc2_ebi-cs-write-address-setup-ns
The property st,fmc2_ebi-cs-write-address-setup-ns should really be
st,fmc2-ebi-cs-write-address-setup-ns (there is underscore _ between
fmc2 and ebi and there should be a dash - instead). This is a remnant
from conversion of old non-upstream bindings. Fix it.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220926222003.527171-1-marex@denx.de
Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers')
| -rw-r--r-- | Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml index 6b516d3895af..a1f535cececc 100644 --- a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml @@ -156,7 +156,7 @@ patternProperties: description: This property defines the data latency before reading or writing the first data in nanoseconds. - st,fmc2_ebi-cs-write-address-setup-ns: + st,fmc2-ebi-cs-write-address-setup-ns: description: This property defines the duration of the address setup phase in nanoseconds used for asynchronous write transactions. |