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author | Kunihiko Hayashi <hayashi.kunihiko@socionext.com> | 2022-03-30 14:23:33 +0900 |
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committer | Rob Herring <robh@kernel.org> | 2022-04-04 19:55:02 -0500 |
commit | d9a64c5eb0e1388c2905961e542b26b2dcae482c (patch) | |
tree | 1e204c82a18e1ac695fb0b6b1be9e4b809984987 /Documentation/devicetree/bindings/pci/socionext,uniphier-pcie.yaml | |
parent | 3123109284176b1532874591f7c81f3837bbdc17 (diff) | |
download | linux-stable-d9a64c5eb0e1388c2905961e542b26b2dcae482c.tar.gz linux-stable-d9a64c5eb0e1388c2905961e542b26b2dcae482c.tar.bz2 linux-stable-d9a64c5eb0e1388c2905961e542b26b2dcae482c.zip |
dt-bindings: PCI: uniphier: Convert uniphier-pcie.txt to json-schema
Convert the file into a JSON description at the yaml format.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1648617814-9217-2-git-send-email-hayashi.kunihiko@socionext.com
Diffstat (limited to 'Documentation/devicetree/bindings/pci/socionext,uniphier-pcie.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/pci/socionext,uniphier-pcie.yaml | 96 |
1 files changed, 96 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie.yaml b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie.yaml new file mode 100644 index 000000000000..f5926d0fb085 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier PCIe host controller + +description: | + UniPhier PCIe host controller is based on the Synopsys DesignWare + PCI core. It shares common features with the PCIe DesignWare core and + inherits common properties defined in + Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. + +maintainers: + - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + enum: + - socionext,uniphier-pcie + + reg: + minItems: 3 + maxItems: 4 + + reg-names: + minItems: 3 + items: + - const: dbi + - const: link + - const: config + - const: atu + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + num-viewport: true + + num-lanes: true + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + +required: + - compatible + - reg + - reg-names + - clocks + - resets + +unevaluatedProperties: false + +examples: + - | + pcie: pcie@66000000 { + compatible = "socionext,uniphier-pcie"; + reg-names = "dbi", "link", "config"; + reg = <0x66000000 0x1000>, <0x66010000 0x10000>, <0x2fff0000 0x10000>; + #address-cells = <3>; + #size-cells = <2>; + clocks = <&sys_clk 24>; + resets = <&sys_rst 24>; + num-lanes = <1>; + num-viewport = <1>; + bus-range = <0x0 0xff>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>, + <0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>; + phy-names = "pcie-phy"; + phys = <&pcie_phy>; + #interrupt-cells = <1>; + interrupt-names = "dma", "msi"; + interrupts = <0 224 4>, <0 225 4>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + + pcie_intc: legacy-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <0 226 4>; + }; + }; |